Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders

Abstract

Irreversible logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its corresponding output vector. Reversible logic circuit naturally takes care of heating because it implements only the functions that have one-to-one mapping between its input and output vectors. Therefore reversible logic design becomes one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power CMOS design, digital signal processing and nanotechnology. This paper presents the efficient approaches for designing reversible fast adders that implement carry look-ahead and carry-skip logic. The proposed 16-bit high speed reversible adder will include IG gates for the realization of its basic building block. The IG gate is universal in the sense that it can be used to synthesize any arbitrary Booleanfunctions. The IG gate is parity preserving, that is, the parity of the inputs matches the parity of the outputs. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. Therefore, the proposed high speed adders will have the inherent opportunity of detecting errors in its output side. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.

Fault Tolerant Variable Block Carry Skip Logic(VBCSL) Using Parity Preserving ReversibleGates

“…The Fig. 13 shows a reversible logic implementation of a 4-bit fault tolerant carry skip adder block proposed in [17]. The block carry input in c is propagated as the block carry output out c , if the block propagate P is one.…”

“…It has been proved in [9][10] that a fault tolerant reversible full adder circuit requires at least three garbage outputs and two constant inputs. This paper will use MIG gate for fault tolerant reversible full adder implementation as used in [17] and will thereby minimize the hardware complexity of the presented systems. The Fig.…”

“…Let α = A two input EXOR gate calculation β = A two input AND gate calculation δ= A NOT gate calculation T = Total logical calculation The total logical calculation of the CSA presented in [15] and [17] are T= 48α+96β+24δ and T=40α+28β+12δ respectively. On the contrary, the total logical calculation of the presented CSAs in this study are T=37α+29β+12δ (Fig.…”

“…The carry skip logic in Fig. 14 has been developed using 3 NFTs and 1 FRG instead of 4 NFTs and 1 F2G as in [17]. The carry skip logic in Fig.…”

“…The fourth one can be considered as garbage if we wish to replace PG by IG. The fourth output line of IG gate can also be minimized to reduce the hardware complexity in [17] as follows:…”