Fault-tolerant sub-lithographic design with rollback recovery

Naeimi, Helia; DeHon, André

doi:10.1088/0957-4484/19/11/115708

Cited by 11 publications

(7 citation statements)

References 46 publications

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“…The factor of 2 avoids double counting gates. In [8], n is 10-100 and c < 10, so the conservative upper bound will be an order of magnitude or two higher than the optimistic lower bound above. Finally, we quantify the implications for the 2016 component with 10 Billion logic transistors and a 10GHz clock.…”

Section: Analysis and Quantificationmentioning

confidence: 91%

“…Using n = 100 and assuming P s = 1 as the best case scenario representing the most frequent exercise of the mismatch case and considering P tu = 10 −18 , a transient error rate which can be tolerated using duplication and checking [8], we get P s mismatch = 2 × 10 −16 . The checkers for this scenario are likely to make up 1-10% of the logic.…”

Section: Infrequently Sensitized Checkersmentioning

confidence: 99%

“…We assume a fine-grained reconfigurable substrate such as the nanoPLA [4] which can easily deal with individual crosspoint and wire defects in the 10% range using matching [5]. Logic is decomposed into small blocks, duplicated, and compared at the bit level to detect transient upsets or lifetime failures [8]; streaming buffers separate computational blocks and facilitate rollback and retry once an error has been detected. A watchdog circuit counts rollbacks and invokes diagnosis and reconfiguration repair when too many rollbacks occur.…”

Section: Introductionmentioning

confidence: 99%

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The Case for Reconfigurable Components with Logic Scrubbing: Regular Hygiene Keeps Logic FIT (Low)

DeHon

2008

2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems

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As we approach atomic-scale logic, we must accommodate an increased rate of manufacturing defects, transient upsets, and in-field persistent failures. High defect rates demand reconfiguration to avoid defective components, and transient upsets demand online error detection to catch failures. Combining these techniques we can detect in-field persistent failures when they occur and reconfigure around them. However, since failures may be logically masked for long periods of time, persistent failures may accumulate silently; this integration of errors over time means the effective failure rate for persistent errors can exceed transient upset rates. As a result, logic scrubbing is necessary to prevent the silent accumulation of an undetectable number of persistent errors. We provide simple analysis to illustrate quantitatively how this phenomena can be a concern. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. andre@computer.org AbstractAs we approach atomic-scale logic, we must accommodate an increased rate of manufacturing defects, transient upsets, and in-field persistent failures. High defect rates demand reconfiguration to avoid defective components, and transient upsets demand online error detection to catch failures. Combining these techniques we can detect in-field persistent failures when they occur and reconfigure around them. However, since failures may be logically masked for long periods of time, persistent failures may accumulate silently; this integration of errors over time means the effective failure rate for persistent errors can exceed transient upset rates. As a result, logic scrubbing is necessary to prevent the silent accumulation of an undetectable number of persistent errors. We provide simple analysis to illustrate quantitatively how this phenomena can be a concern.

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Section: Analysis and Quantificationmentioning

confidence: 91%

Section: Infrequently Sensitized Checkersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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The Case for Reconfigurable Components with Logic Scrubbing: Regular Hygiene Keeps Logic FIT (Low)

DeHon

2008

2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems

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“…To tackle (with minimal power/performance overhead) the errors manifesting due to ever-increasing unreliability of the CMOS devices, various circuit-level mechanisms including redundant latches/paths [14], [15], [16], [17], [18], slack redistribution [19], and confidence-driven computation [20] have been proposed.…”

Section: Related Workmentioning

confidence: 99%

Energy-efficient pass-transistor-logic using decision feedback equalization

Takhirov¹,

Nazer²,

Joshi³

2013

International Symposium on Low Power Electronics and Design (ISLPED)

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Decision feedback equalization (DFE) has been used to improve energy efficiency and/or reduce error rate in communication links. We propose a novel circuit technique which applies DFE techniques to pass transistor logic (PTL)-based computational circuits to mitigate errors, and reduce energy per computation or improve performance. We also present an optimization framework for designing low energy equalized PTL circuits that meet target performance and error rate specifications. On average, for the same operating frequency and error rate, the equalized PTL design consumes between 15% and 30% lower energy per operation than PTL and static complementary logic, respectively.

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“…The joint application of both reconfiguration and NAND multiplexing in Han and Jonker [2003] exploits the advantage of both techniques to further reduce redundancy by a factor of 10. In addition to spatial redundancy, methods relying on temporal redundancy (e.g., rollback [Mizan 2007;Naeimi and DeHon 2008]) are effective when the error rate is low. ECC is commonly employed to provide fault tolerance for nanoscale memories and interconnects [Kuekes et al 2005;Strukov and Likharev 2007;Sun et al 2008].…”

Section: Introductionmentioning

confidence: 99%

A defect/error-tolerant nanosystem architecture for DSP

Tang

Wang

Lombardi

2009

J. Emerg. Technol. Comput. Syst.

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Emerging technologies such as silicon NanoWires (NW) and Carbon NanoTubes (CNT) have shown great potential for building the next generation of computing systems in the nano ranges. However, the excessive number of defects originating from bottom-up fabrication (such as a self-assembly process) poses a pressing challenge for achieving scalable system integration. This article proposes a new nanosystem architecture that employs nanowire crossbars for Digital Signal Processing (DSP) applications. Distributed arithmetic is utilized such that complex signal processing computation can be mapped into regular memory operations, thus making this architecture well suited for implementation by nanowire crossbars. Furthermore, the inherent features of DSP-type computation provide new insights to remedy errors (as logic/computational manifestation of defects). A new defect/error-tolerant technique that exploits algorithmic error compensation is proposed; at system level different trade-offs between correctness in output and performance are established while retaining low overhead in its implementation. As an instance of its application, the proposed approach has been utilized to a generic DSP nanosystem performing frequency-selective filtering. Simulation results show that the proposed nanoDSP introduces only a minor performance degradation under high defect rates and at a range of operational conditions. The proposed technique also features good scalability and viability for various DSP applications.Some preliminary results of this work were reported in the International Symposium on Nanoscale Architectures (NANOARCH) 2008 [Tang andWang 2008].

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Fault-tolerant sub-lithographic design with rollback recovery

Cited by 11 publications

References 46 publications

The Case for Reconfigurable Components with Logic Scrubbing: Regular Hygiene Keeps Logic FIT (Low)

The Case for Reconfigurable Components with Logic Scrubbing: Regular Hygiene Keeps Logic FIT (Low)

Energy-efficient pass-transistor-logic using decision feedback equalization

A defect/error-tolerant nanosystem architecture for DSP

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