Fault-tolerant TMR and DMR circuits with latchup protection switches

Petrović, Vladimir; Schoof, Gunter; Stamenković, Zoran

doi:10.1016/j.microrel.2014.04.001

Cited by 21 publications

(12 citation statements)

References 19 publications

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“…A SEL protection switch (SPS cell) based on the principle of power domain control has been designed and developed in the IHP 250 nm bulk CMOS technology, and evaluated through simulations and irradiation experiments [23,[34][35][36][37]. A SPS cell has also been recently developed in the IHP 130 nm bulk CMOS process.…”

Section: Sps Cell Design and Operationmentioning

confidence: 99%

“…The design depicted in Fig. 4 is a slight modification of the version presented in [37], but the two versions have the same functionality. Namely, to reduce the power consumption of the SPS cell, the resistors that were implemented in the design reported in [37] have been replaced with transistors.…”

Section: Sps Cell Design and Operationmentioning

confidence: 99%

“…4 is a slight modification of the version presented in [37], but the two versions have the same functionality. Namely, to reduce the power consumption of the SPS cell, the resistors that were implemented in the design reported in [37] have been replaced with transistors. The following discussion gives a brief explanation of the SPS cell operating principle required for understanding the simulation procedure and obtained results, while more detailed discussion can be found in [23,[34][35][36][37].…”

Section: Sps Cell Design and Operationmentioning

confidence: 99%

“…The operation of the SPS in the case of SEL was investigated extensively through the circuit-level simulations [23,[34][35][36][37]. In addition, the irradiation tests have been conducted to evaluate the performance of the SPS cell under real irradiation conditions similar to those encountered in the space environment.…”

Section: Sps Cell Design and Operationmentioning

confidence: 99%

“…Using the transistor-based SEL sensing approach, an onchip SEL protection switch (SPS cell) for CMOS integrated circuits has been previously designed and developed in the IHP 250 nm CMOS technology [23,[34][35][36][37]. The SPS cell has been initially tested through the circuit level simulation and its functionality has been validated in the normal mode and in the case of SEL.…”

Section: Introductionmentioning

confidence: 99%

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Circuit-Level Simulation of the Single Event Transients in an On-Chip Single Event Latchup Protection Switch

et al. 2015

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The circuit-level simulation analysis of the single event transient response of an on-chip single event latchup protection switch (SPS cell), previously designed and developed in the IHP 250 nm CMOS process, is presented. The SPS cell provides the latchup protection for standard cells on the principle of power domain control. It is based on a sensing/ driving PMOS transistor which acts both as a latchup sensor and a driver for the standard cells, and includes additional PMOS and NMOS transistors for controlling the sensing/ driving transistor and interfacing to the external control logic. The previous work has confirmed the SPS cell's functionality in the case of single event latchup, and the experimental investigation has proven that the SPS cell is immune to single event latchup for LET values up to 74.8 MeV cm 2 /mg. This case study extends the previous research by introducing the circuit-level simulation of the SPS cell's response to the single event transients (SETs). Using the square pulse current as a SET model, the amplitude and duration of the SET-induced voltage pulses at the SPS cell's outputs have been analyzed with respect to the injected charge, operating temperature, supply voltage, load (number of standard cells connected to the SPS cell) and sensing/driving transistor's channel width. The results have shown that the immunity of the SPS cell to SETs can be significantly enhanced by connecting a larger number of standard cells to the SPS cell and increasing the sensing/driving transistor's size, without any area overhead.An analytical expression for calculating the critical charge in terms of the transistor size and the number of standard cells connected to the SPS cell has been derived. Moreover, the SPS cell can be used as a SET sensor for detecting the levels of injected charge which cannot be mitigated by the increase of transistor size and load, and in conjunction with the external control logic it could be possible to measure the SET duration and perform online corrections of the SET-induced faults in the standard cells supplied by the SPS cell.

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Section: Sps Cell Design and Operationmentioning

confidence: 99%

Section: Sps Cell Design and Operationmentioning

confidence: 99%