Feasibility of fixed-point transversal adaptive filters in FPGA devices with embedded DSP blocks

Abstract

Transversal adaptive filters for digital signal processing have traditionally been implemented into DSP processors due to their ability to perform fast floating-point arithmetic. However, with its growing die size as well as incorporating the embedded DSP block, the FPGA devices have become a serious contender in the signal processing market. Although it is not yet feasible to use floating-point arithmetic in modern FPGAs, it is sufficient to use fixed-point arithmetic and still achieve tap-weight convergence for adaptive filters. This paper examines the feasibility of implementing an adaptive algorithm, namely the LMS algorithm, based on fixed-point arithmetic, using the Altera Stratix device.

FPGA Implementation of Adaptive Noise Canceller

“…It requires neither measurement of the correlation function, nor matrix inversion [4] .It uses Mean Square Error (MSE) as a criterion. LMS uses a step-size parameter, input signal and the difference of desired signal and filter output signal to frequently calculate the update of the filter coefficients set [3].…”

“…Selection of Adaptive Parameters: The choice of the step-size parameter and the order of the filter effectively determines the performance of LMS [3]. From Eq.…”

“…Unfortunately, there is no clear mathematical analysis to derive the exact quantities. Only through experiments may a reasonable solution be obtained [3]. In order to select appropriate step size and filter order, MATLAB simulation of LMS algorithm is carried out.…”

“…Since FPGA consists of slices organized as array of rows and columns, a great deal of parallelism can be explored. Although it is not efficient to use floating-point arithmetic in FPGA due to its need for a large area ,it is sufficient to use fixed-point arithmetic for the adaptive filter to work well [3]. In general FIR structure has been used more successfully than IIR structure in adaptive filters [4].…”

Real Time Implementation of Fir Filter Based on Time Delay Neural Network

“…In section 5, the hardware implementation of the TDNN and its proposed hardware architecture is presented. Finally, in section 6, the experimental results and a comparison with the system presented in [5] where an FPGA chip is used to emulate an adaptive FIR filter of various taps length is performed. Also some conclusions are discussed in this section.…”