Feature extraction without learning in an analog spatial pooler memristive-CMOS circuit design of hierarchical temporal memory

Krestinskaya, Olga; James, Alex Pappachen

doi:10.1007/s10470-018-1161-1

Cited by 22 publications

(12 citation statements)

References 11 publications

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“…The main advantage of this model is in ability of programming limits of sigmoid by adjusting two bias currents [8]. As the memristor is a promising solution used in various architectures [9], [10], [11], [12], [13], [14], introducing memristors further improves the circuit is terms of on-chip area and power dissipation. This paper is structured in the following way: Section 1 gives an introduction to the article, Section 2 goes through the background information about the existing projects, in the third section Methodology is discussed, Results and Discussions are provided in the fourth section, and finally Conclusion will be drawn based on results and performed work.…”

Section: Introductionmentioning

confidence: 99%

Notice of Retraction: Variability Analysis of Memristor-based Sigmoid Function

Kaiyrbekov

Krestinskaya

James

2018

2018 International Conference on Computing and Network Communications (CoCoNet)

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Activation functions are widely used in neural networks to decide the activation value of the neural unit based upon linear combinations of the weighted inputs. The effective implementation of activation function is highly important, as they help to represent non-linear complex functional mappings between inputs and outputs of the neural network. One of the non-linear approaches is to use a sigmoid function. Therefore, there is a growing need in enhancing the performance of sigmoid circuits. In this paper, the main objective is to modify existing current mirror based sigmoid model by replacing CMOS transistors with memristor devices. This model was tested varying different circuit parameters, transistor size and temperature. The the area, power and noise in the modified CMOS-memristive sigmoid circuit are shown. The application of memristors in the sigmoid circuit results in higher component density in an onchip area, allowing a reduction of power and area by 7%. The proposed sigmoid circuit was simulated in SPICE using 180nm TSMC CMOS technology.

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Section: Introductionmentioning

confidence: 99%

Notice of Retraction: Variability Analysis of Memristor-based Sigmoid Function

Kaiyrbekov

Krestinskaya

James

2018

2018 International Conference on Computing and Network Communications (CoCoNet)

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“…More recently, systems able of solving different tasks, such as speech recognition (Park et al, 2015 ), and exploring different architectures and learning algorithms are being investigated. In particular, the benefits of exploiting sparsity, mentioned in section 3.2, are demonstrated for feature extraction and image classification in networks trained with stochastic gradient descend and winner-take-all learning algorithms (Sheridan et al, 2016 ), as well as in hierarchical temporal memory, which does not need training (Krestinskaya and James, 2018 ).…”

Section: Memristive Devices and Computingmentioning

confidence: 99%

Adaptive Extreme Edge Computing for Wearable Devices

et al. 2021

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Wearable devices are a fast-growing technology with impact on personal healthcare for both society and economy. Due to the widespread of sensors in pervasive and distributed networks, power consumption, processing speed, and system adaptation are vital in future smart wearable devices. The visioning and forecasting of how to bring computation to the edge in smart sensors have already begun, with an aspiration to provide adaptive extreme edge computing. Here, we provide a holistic view of hardware and theoretical solutions toward smart wearable devices that can provide guidance to research in this pervasive computing era. We propose various solutions for biologically plausible models for continual learning in neuromorphic computing technologies for wearable sensors. To envision this concept, we provide a systematic outline in which prospective low power and low latency scenarios of wearable sensors in neuromorphic platforms are expected. We successively describe vital potential landscapes of neuromorphic processors exploiting complementary metal-oxide semiconductors (CMOS) and emerging memory technologies (e.g., memristive devices). Furthermore, we evaluate the requirements for edge computing within wearable devices in terms of footprint, power consumption, latency, and data size. We additionally investigate the challenges beyond neuromorphic computing hardware, algorithms and devices that could impede enhancement of adaptive edge computing in smart wearable devices.

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“…The system level simulation results show that this approach allows to preserve feature sparsity and increase for recognition accuracy for face recognition problems. The hardware implementation of [30] is shown in [31]. Comparing to the HTM SP implementation in [12], modified HTM SP receptor block involves memristive mean calculation circuit, CMOS comparator and CMOS analog switch.…”

Section: Circuitmentioning

confidence: 99%

“…The HTM TM circuit is presented for a single pixel implementation. The real time Algorithm modification of HTM SP [12] with hardware testing [31] Analog HTM SP modified design of [12], modified algorithm in [30], hardware testing [31] Face recognition up to 98 % Single receptor block:…”

Section: B Limitations Of Memristive Htm Hardware Implementationmentioning

confidence: 99%

Hierarchical Temporal Memory Using Memristor Networks: A Survey

Krestinskaya

Dolzhikova

James

2018

IEEE Trans. Emerg. Top. Comput. Intell.

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This paper presents a survey of the currently available hardware designs for implementation of the human cortex inspired algorithm, Hierarchical Temporal Memory (HTM). In this review, we focus on the state of the art advances of memristive HTM implementation and related HTM applications. With the advent of edge computing, HTM can be a potential algorithm to implement on-chip near sensor data processing. The comparison of analog memristive circuit implementations with the digital and mixed-signal solutions are provided. The advantages of memristive HTM over digital implementations against performance metrics such as processing speed, reduced on-chip area and power dissipation are discussed. The limitations and open problems concerning the memristive HTM, such as the design scalability, sneak currents, leakage, parasitic effects, lack of the analog learning circuits implementations and unreliability of the memristive devices integrated with CMOS circuits are also discussed.

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Feature extraction without learning in an analog spatial pooler memristive-CMOS circuit design of hierarchical temporal memory

Cited by 22 publications

References 11 publications

Notice of Retraction: Variability Analysis of Memristor-based Sigmoid Function

Notice of Retraction: Variability Analysis of Memristor-based Sigmoid Function

Adaptive Extreme Edge Computing for Wearable Devices

Hierarchical Temporal Memory Using Memristor Networks: A Survey

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