Features of the Digital Block of a Hardware Simulator for MIMO Radio Channels

Abstract

The aim of the French regional research project SIMPAA2, which continues the former national research SIMPAA project, is the realization of a hardware simulator of MIMO propagation channels for UMTS and WLAN applications. The simulator must reproduce the behavior of the radio propagation channel, thus making it possible to test "on table" the mobile radio equipments. The advantages are: low cost, short test duration, possibility to ensure the same test conditions in order to compare the performance of various equipments. Two digital architectures are proposed and analyzed depending on the different environment characteristics.

Outdoor-to-Indoor MIMO Hardware Simulator with Channel Sounding at 3.5 GHz

“…However, theoretical models of timevarying channels can be obtained using Rayleigh fading [10]. At IETR, several architectures of the digital block of a hardware simulator have been studied [11,12]. Typically, radio propagation channels are simulated using finite impulse response (FIR) filters, as in [11,12,14].…”

“…At IETR, several architectures of the digital block of a hardware simulator have been studied [11,12]. Typically, radio propagation channels are simulated using finite impulse response (FIR) filters, as in [11,12,14]. The Fast Fourier Transform (FFT) modules can also be used to obtain an algebraic product, as in [11,13].…”

“…Typically, radio propagation channels are simulated using finite impulse response (FIR) filters, as in [11,12,14]. The Fast Fourier Transform (FFT) modules can also be used to obtain an algebraic product, as in [11,13]. In [15], a method fitting the cross-correlation matrix to the estimated matrix of a real-world channel was presented.…”

“…The frequency architecture considered in [11,13] operates correctly for signals not exceeding the FFT size. Thus, new frequency architecture avoiding this limitation has been presented and tested in [16].…”

“…• The time domain architecture presented in [11,12,14] has an occupation of 11 to 13 % of slices on the FPGA for one SISO channel. In this paper, we present a time domain architecture with an occupation of 5 % for one SISO channel and up to 80 % for MIMO 4×4.…”