Feedback-controlled enhance-pull-down BiCMOS for sub-3-V digital circuit

Abstract

This paper describes a new feedbackcontrolled ehanced-pull-down BiCMOS (FC-EPD-BiCMOS) logic scheme for the low-supply-voltage operation. Through the use of the feedback-controlled enhanced-pull-down structure, the driving capability is improved and biploar transistor saturation during operation period is avoided. Based upon the proposed structure, both static and differential logic gates are developed. The new BiCMOS three-input NAND gate offers 35% reduction in the propagation delay time as compared to conventional BiCMOS circuits at 2.5 V supply voltage. The proposed three-input FC-EPD-BiCMOS CPL XORlXNOR gate has 33% improvement in delay time as compared to conventional BiCMOS 3input XORKNOR gates at 2.4 V supply voltage.