FELIX: The new detector readout system for the ATLAS experiment

Ryu, S.

doi:10.1088/1742-6596/898/3/032057

Cited by 12 publications

(11 citation statements)

References 9 publications

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“…Figure 2 shows the eye diagram of a 1-hour test for a high-speed communication that we have carried out to validate the GBT protocol over the SFP connector. These tests are performed also to integrate our work within the ATLAS TDAQ collaboration and in particular with the FELIX group, so to interface with electronic boards called FELIX [8][9]. Eventually the…”

Section: Testsmentioning

confidence: 99%

A Multi-Channel PCI Express Readout Board Proposal for the Pixel Upgrade at LHC

Gabrielli¹,

Alfonsi²,

D’amen³

et al. 2018

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP-17)

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Section: Testsmentioning

confidence: 99%

A Multi-Channel PCI Express Readout Board Proposal for the Pixel Upgrade at LHC

Gabrielli¹,

Alfonsi²,

D’amen³

et al. 2018

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP-17)

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“…A dedicated custom-hardware electronics system, known as Level-0, will perform the initial reduction from the collision rate of 40 MHz to 1 MHz. Upon selection by the Level-0, data from the detector sensors are pushed through approximately 17000 highspeed serial links into FELIX [16]. FELIX acts as interface between these links and a general purpose network.…”

Section: Atlas Upgrade Designmentioning

confidence: 99%

Buffer Provisioning for Large-Scale Data-Acquisition Systems

Santos

Vandelli

García

et al. 2018

Proceedings of the 12th ACM International Conference on Distributed and Event-Based Systems

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The data acquisition system of the ATLAS experiment, a major experiment of the Large Hadron Collider (LHC) at CERN, will go through a major upgrade in the next decade. The upgrade is driven by experimental physics requirements, calling for increased data rates on the order of 6 TB/s. By contrast, the data rate of the existing system is 160 GB/s. Among the changes in the upgraded system will be a very large buffer with a projected size on the order of 70 PB. The buffer role will be decoupling of data production from on-line data processing, storing data for periods of up to 24 hours until it can be analyzed by the event processing system. The larger buffer will allow a new data recording strategy, providing additional margins to handle variable data rates. At the same time it will provide sensible trade-offs between buffering space and on-line processing capabilities. This compromise between two resources will be possible since the data production cycle includes time periods where the experiment will not produce data. In this paper we analyze the consequences of such trade-offs, and introduce a tool that allows a detailed exploration of different strategies for resource provisioning. It is based on a model of the upgraded data acquisition system, implemented in a simulation framework. From this model it is possible to obtain insight into the dynamics of the running system. Given predefined resource constraints, we provide bounds for the provisioning of buffering space and on-line processing requirements.

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“…The third data path at the bottom of figure 2 with components shown in white boxes is for the common Level-1 readout and slow control chain. Hit charge and time information from NSW detectors are held at the Readout Controller (ROC) ASIC [14] until the Level-1 acceptance and then data are shifted out to the Front-end link exchange (FELIX) unit [13] where they are recognized and passed to the succeeding Readout Driver (ROD) for event building. This data path also includes bidirectional links via the FELIX interface.…”

Section: Nsw Upgrade and Its Readout Schemementioning

confidence: 99%

Trigger algorithms and electronics for the ATLAS muon new small wheel upgrade

Guan

2016

J. Inst.

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FELIX: The new detector readout system for the ATLAS experiment

Cited by 12 publications

References 9 publications

A Multi-Channel PCI Express Readout Board Proposal for the Pixel Upgrade at LHC

A Multi-Channel PCI Express Readout Board Proposal for the Pixel Upgrade at LHC

Buffer Provisioning for Large-Scale Data-Acquisition Systems

Trigger algorithms and electronics for the ATLAS muon new small wheel upgrade

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