Ferroelectric 1-T memory device—will it be viable for nonvolatile memory applications?

Abstract

The quest for a nonvolatile memory FET based on the metal-ferroelectric-(insulator)semiconductor (MF(I)S) gate stack concept has greatly intensified in recent years. In principle, such a memory device (MF(I)S) could be a building block of an ideal memory technology which offers random access, high speed, low power, high density and non-volatility. In practice, however, none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days so far. These results are a far cry from the 10-year retention time requirement for non-volatile memory devices. This paper reveals progress and optimization that grain size, interfacial properties, and crystallinity of the annealed ferroelectric SrBi 2 Ta 2 O 9 (SBT) films have a strong impact on the size of the memory window, as does the choice of the buffer layer material. The properties of SiN buffer layer sandwiched between SBT and Si are discussed. Switches in the polarization of the ferroelectric SBT play a key role for both the ferroelectricpolarization-dominated and the trapping-dominated memory windows. Preliminary results on MFIS capacitors and transistors are reviewed, limited retention time has been observed. A closer look at the physics of device operation reveals two major causes of the short retention time: (1) depolarization fields; (2) finite gate leakage current and the associated charge trapping. Here, the origins of these problems are analyzed and practical difficulties in attempting to realize nonvolatile ferroelectric 1-T memory devices are illustrated. Two possible solutions have been proposed to circumvent problems associated with the finite retention time in ferroelectric FETtype memories: (1) memory refreshes as done in the FEDRAM cell, (2) single-crystallize the ferroelectric film. * Currently working at Infineon/IBM Alliance 45nm technology R&D project email: jh262@ieee.org.