Ferroelectric-Gated All 2D Field-Effect Transistors with Sub-60 mV/dec Subthreshold Swing

Liu, Zhongyang; Sun, Yilin; Ding, Yingtao; Li, Mingjie; Liu, Xiao; Liu, Zhifang; Chen, Zhiming

doi:10.1021/acs.jpclett.3c01463

Cited by 2 publications

(1 citation statement)

References 60 publications

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“…For the conventional metaloxide semiconductor field effect transistors (MOSFET), 60 mV dec −1 SS value is at best reported at room temperature [33]. However, improved SS values as small as 25 mV dec −1 is also being achieved in non-conventional hybrid transistors and day by day the limit is reducing [34,35]. As can be seen from the figure 2(b), the SS value lowers rapidly with the increase in the gate width from 10 to 30 nm, while saturates later below the SS value equal to 0.4 V dec −1 , which shows that the simulated orgnic transistors have still compromised SS values compared to the conventional MOSFETs and needs improvement in order to advance organic electronics However, when compared to the experimental results on fabricated organic transsistors based on PTCDI-C8 without graphene as a source electrode, the simulated results with perforated graphene as source electrodes show improvement in reducing the SS values [36,37].…”

Section: Source Electrode Perforation Size/gate Openingmentioning

confidence: 99%

Predicting the miniaturization limit of vertical organic field effect transistor (VOFET) with perforated graphene as a source electrode

Shukla,

Bisht,

Kumar

2023

Nanotechnology

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Vertical organic field effect transistors (VOFETs) are of paramount importance due to their fast switching speed, low power consumption, and higher density on a chip compared to lateral OFETs. The low charge carrier mobility in organic semiconductors and longer channel lengths in lateral OFETs lead to higher operating voltages. The channel length in VOFETs can be less than 100 nm which reduces the size of the channel and hence the operating voltages. Another important factor in the operation of VOFETs is the thickness and width of the source electrode. The channel length, source electrode thickness, and width sets the miniaturization limit of the VOFETs. The graphene monolayer can be exploited as a source electrode due to its thinness, high carrier mobility, and metallic behaviors. However, for better gate modulation, perforations in the source material are desired. Here, we simulate the VOFET having perforated graphene monolayer as a source electrode and n-type organic semiconductor N, N′-dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C8) as an active channel material, while aluminum as a drain electrode to predict the best-miniaturized device. The miniaturization limit of such a VOFET has a limit to the gate opening/perforation in which the minimum source width is 10 nm, as in the sub 10 nm range graphene starts behaving like a semiconductor. The subthreshold swing, deduced from the drain current (JD) vs gate voltage (VG) graph, advocates the limit of the organic semiconductor height/channel length to 50 nm, while 50 nm for the gate.

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Section: Source Electrode Perforation Size/gate Openingmentioning

confidence: 99%

Predicting the miniaturization limit of vertical organic field effect transistor (VOFET) with perforated graphene as a source electrode

Shukla,

Bisht,

Kumar

2023

Nanotechnology

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2D Steep‐Slope Tunnel Field‐Effect Transistors Tuned by van der Waals Ferroelectrics

Chen,

Jiang,

Wang

et al. 2024

Adv Elect Materials

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AbstractsPower consumption has emerged as a central concern in the realm of complementary metal‐oxide‐semiconductor (CMOS) technology. Silicon‐based semiconductor devices have now approached the fundamental thermionic limit of the subthreshold swing (SS), which is 60 mV dec−1, as defined by the Boltzmann tyranny. Tunnel field‐effect transistors (TFETs) are considered promising low‐power devices due to the band‐to‐band tunneling mechanism, which effectively avoids the thermionic limit. However, TFETs require the establishment of a staggered band alignment and currently lack effective techniques for adjusting the band offset. Here, by harnessing the robust ferroelectric field inherent to 2D CuInP2S6 (CIPS), a 2D WSe2/MoS2 heterojunction as well as a WSe2 homojunction TFET controlled by ferroelectric gate are presented. The newly developed TFET achieves an ultra‐low SS of 14.2 mV dec−1 at room temperature, an on/off current ratio exceeding 108, and a minimal hysteresis window below 10 mV. Additionally, the device demonstrates gate tunable negative differential resistance (NDR) characteristics with a very large peak‐to‐valley current ratio (PVCR) of 10.56 at room temperature. These findings underscore the significant promise of 2D ferroelectric tuning heterojunction and homojunction for future low‐power electronic applications.

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Ferroelectric-Gated All 2D Field-Effect Transistors with Sub-60 mV/dec Subthreshold Swing

Cited by 2 publications

References 60 publications

Predicting the miniaturization limit of vertical organic field effect transistor (VOFET) with perforated graphene as a source electrode

Predicting the miniaturization limit of vertical organic field effect transistor (VOFET) with perforated graphene as a source electrode

2D Steep‐Slope Tunnel Field‐Effect Transistors Tuned by van der Waals Ferroelectrics

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