Field‐programmable gate array‐based design for real‐time computation of ensemble empirical mode decomposition

Abstract

Empirical mode decomposition (EMD) is considered as a suitable method when the signal to be analyzed is nonlinear or nonstationary in nature. But, EMD suffers from a problem known as mode mixing. To, reduce this problem, ensemble EMD (EEMD) was proposed. In this paper, we have presented a fast field-programmable gate array (FPGA)-based design for EEMD. Where calculation of output can be done in a parallel manner for different realizations.The design has a comparatively less execution time, and the execution time of the proposed EEMD design is even less than some state-of-the-art EMD-based design, although the architecture of EEMD is more complex, when compared with the EMD design. In this work, we have also performed an FPGA implementation of the EMD algorithm. The root mean square error (RMSE) and the correlation values of the intrinsic mode function (IMFs) obtained from the proposed EMD and EEMD designs are compared. The proposed FPGA-based architecture of the EEMD algorithm is designed using Verilog-hardware description language (HDL) and implemented on a Kintex-7 FPGA. The EEMD architecture consists of cubic Hermite spline interpolation (CHSI) and cubic spline interpolation (CSI) for the envelope generation. K E Y W O R D Sempirical mode decomposition (EMD), ensemble empirical mode decomposition (EEMD), field-programmable gate array (FPGA), parallel architectures