Fifth- and Seventh-Order Harmonic Elimination With Multilevel Dodecagonal Voltage Space Vector Structure for IM Drive Using a Single DC Source for the Full Speed Range

Boby, Mathews; Pramanick, Sumit; Kaarthik, R. Sudharshan; S, Arun Rahul; Gopakumar, K.; Umanand, L.

doi:10.1109/tpel.2016.2528305

Cited by 27 publications

(4 citation statements)

References 19 publications

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“…Out of these, the basic sinusoidal pulse width modulation (SPWM) helps in generating the sinusoidal fundamental voltage across the phase windings. However, the fundamental peak value of phase voltage obtained using SPWM is 0.5

V_{dc} .

10 Later, a hexagonal SVPWM technique for the three‐phase IMD is presented in Reference 11 to improve the LMR by 15.4% with respect to SPWM and as a result the fundamental peak value of phase voltage obtained is 0.577

V_{dc} .

12 Alternatively, different inverter topologies are presented in the literature to develop the dodecagonal and octadecagonal space vector structures for the three‐phase IMD which helps in achieving improved DC‐link utilization and better torque profile 13,14,15 . However, these topologies require higher count of semiconductor switches and isolated DC voltage sources of multiple ratings.…”

Section: Introductionmentioning

confidence: 99%

18‐Sided polygon voltage space vector fed nine‐phase induction machine drive for high power applications

Vemula

Keerthipati

2021

Int Trans Electr Energ Syst

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The advantages such as better fault‐tolerant capability, less space harmonic content, and requirement of power semiconductor devices with reduced voltage ratings etc., made the multi‐phase induction machines drives (IMD) best desirable for the high power applications. However, as the number of phase increases, the improvement in the LMR of the multi‐phase IMDs is not significant using the conventional SVPWM techniques provided in the literature. To address the above‐mentioned limitation, 18‐sided polygon (octadecagon) based voltage space vector generation for a nine‐phase IMD is proposed in this article without compromising in the torque harmonic profile. Using the proposed octadecagonal voltage space vector generation technique, the LMR of nine‐phase IMD is significantly improved by 26.03%, 24.28%, and 9.15% in comparison to the nine‐phase sinusoidal pulse width modulation, nine‐phase SVPWM and individual hexagonal SVPWM techniques, respectively. Efficacy of the proposed control technique is substantiated using the results obtained from ANSYS Maxwell simulation and experimentation on 5‐hp nine‐phase IMD prototype in the laboratory.

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V_{dc} .

V_{dc} .

Section: Introductionmentioning

confidence: 99%

18‐Sided polygon voltage space vector fed nine‐phase induction machine drive for high power applications

Vemula

Keerthipati

2021

Int Trans Electr Energ Syst

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“…Solar cells, energy components, batteries, and ultracapacitors are the most well-known free sources used (Gobinath et al, 2013). The necessity of more than one DC source makes four quadrant processes troublesome while more than one dynamic front end converters are required (Boby et al, 2016). The capacity of a multilevel inverter is to integrate a sought voltage wave shape from a few levels of DC voltages (Keerthana and Jebaraj, 2015).…”

Section: Introductionmentioning

confidence: 99%

Effective utilisation of cascade H-bridge multi level inverter integrate social spider optimisation for reduced total harmonics distortion

Swamy

Beno

2019

IJMTM

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The significance intention of the proposed method is to eliminate total harmonics distortion (THD) in solar photovoltaic cells powered cascaded H-bridge multilevel inverter (CHMLI). This purpose incorporates Newton-Raphson (NR), particle swarm optimisation (PSO), artificial bee colony (ABC), genetic algorithm (GA), cuckoo search (CS) and social spider optimisation (SSO)-based selective harmonic elimination technique for solving a non-linear transcendental equation to obtain optimal switching angle to achieve minimise THD. The foremost goal to reduce THD value beyond IEEE standard allowable limit is to predict optimal switching angle. This prediction is done in offline then it utilises for online simulation process to achieve minimised THD. Amid, aforementioned techniques incorporate with CHMLI; SSO behaves literally better than all other comparative techniques to attain 3.6% of THD in line voltage from the modulation index of 0.95. This customised product development would enhance quality power flow in this power generation.

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“…However, in case of partial shading, there is a chance of having the difference in voltages across the capacitors because of individual MPPT, this may lead to DC offset voltage at AC output voltage. In induction motor drives and UPS applications, the capacitor voltage balancing issues are addressed in [9][10][11][12]. All these techniques are focused to address the difference in the capacitor voltages because of load current.…”

Section: Introductionmentioning

confidence: 99%

DC offset minimisation of three‐phase multilevel inverter configuration under fault and DC link voltage unbalance conditions

Airineni

Keerthipati

2018

IET Power Electronics

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In recent days, multilevel inverters are quite popular in the photovoltaic system to improve the power quality. One of the popular multilevel inverters for medium power applications is neutral point clamping inverter. However, with the limited number of switching combinations, energy balancing and fault-tolerant operation is a major issue. The absence of energy balance mechanism may lead to unequal charge and discharge patterns in the batteries used in off-grid applications, which in turn results in the unequal voltage at the batteries terminals. The difference in voltage between the sources can introduce the DC voltage offset at AC output, which causes serious problems when fed to the transformers or inductive loads like the induction motor. To address this problem, a five-level inverter is proposed which is capable of energy balancing between the two DC sources, minimising the DC voltage offset and able to operate in some fault-tolerant conditions. At the same time, this topology uses less number of switches as compared to conventional three-phase five-level inverters. The proposed topology is developed by combining conventional two-level and three-level inverters. The topology is verified by simulation using Matlab Simulink and tested on a laboratory prototype. The control algorithm for prototype is implemented with the help of Xilinx SPARTAN-6 (XC6SLX9) FPGA board.

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Fifth- and Seventh-Order Harmonic Elimination With Multilevel Dodecagonal Voltage Space Vector Structure for IM Drive Using a Single DC Source for the Full Speed Range

Cited by 27 publications

References 19 publications

18‐Sided polygon voltage space vector fed nine‐phase induction machine drive for high power applications

18‐Sided polygon voltage space vector fed nine‐phase induction machine drive for high power applications

Effective utilisation of cascade H-bridge multi level inverter integrate social spider optimisation for reduced total harmonics distortion

DC offset minimisation of three‐phase multilevel inverter configuration under fault and DC link voltage unbalance conditions

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