Filling TSV of different dimension using galvanic copper deposition

Rohde, Dirk; Jäger, Cornelia; Hazin, Khatera; Uhlig, Albrecht

doi:10.1109/impact.2011.6117182

Cited by 7 publications

(6 citation statements)

References 25 publications

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“…The so-called bottom-up growth mode observed in the filling of high aspect ratio TSVs has attracted much attention. [3][4][5][6] This growth mode is quite different from the previously known super-conformal "zip-fill" mode. 1,2 In the bottom-up growth mode, the flat bottom grows significantly faster than the top and lateral surface.…”

contrasting

confidence: 63%

The Limitation and Optimization of Bottom-Up Growth Mode in Through Silicon Via Electroplating

Liu

Radisic

Deconinck

et al. 2015

J. Electrochem. Soc.

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An analytical model is developed for the bottom-up growth mode observed in the electroplating of high aspect ratio through-silicon vias (TSVs). The effects of various factors, including the feature geometry, the suppression effect of the suppressive additives and the applied electric current, on the filling process are discussed. The process window for void-free filling and its narrowing down with the reduction of TSV footprint are demonstrated in simulation. The motivation to introduce ramping current in the electroplating of high aspect ratio TSVs is analyzed. Reduced plating time is demonstrated for stepwise ramping of the input current. Using the proposed analytical model, a simulation methodology for fast searching of the optimal plating conditions in multiple-step plating schemes is introduced.

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contrasting

confidence: 63%

The Limitation and Optimization of Bottom-Up Growth Mode in Through Silicon Via Electroplating

Liu

Radisic

Deconinck

et al. 2015

J. Electrochem. Soc.

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“…The phenomena causing these defects have been studied and the underlying physics has been explained in the literature [43,44]. The studies also propose new design and manufacturing techniques to avoid these defects, for instance Layout optimization for reduced mechanical stress [45], Layout optimization with respect to carrier mobility variations near TSVs [40], Void-free filling techniques [46].…”

Section: Voids In Tsvsmentioning

confidence: 99%

“…Voids, as shown in Figure 3.1 are formed due to insufficient filling [46]. A pinhole is an oxide defect that creates a short between the TSV and the substrate [34].…”

Section: Contactless Pre-bond Tsv Test and Diagnosis Using Ring Oscilmentioning

confidence: 99%

Test and debug solutions for 3D-stacked integrated circuits

Deutsch

Chakrabarty

2015

2015 IEEE International Test Conference (ITC)

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Three-dimensional (3D) stacking using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moore's law. TSVs are small copper or tungsten vias that go vertically through the substrate of a die and provide vertical interconnects to a die stacked on top. TSV-based interconnects have benefits in terms of performance, interconnect density, and power efficiency.Testing has been identified as a showstopper for volume manufacturing of 3D-stacked integrated circuits (3D ICs). A number of challenges associated with 3D test need to be addressed before 3D ICs can become economically viable. This dissertation provides solutions to new challenges related to 3D test content, test access, diagnosis and debug.Test content specific to 3D ICs targets defect that occur during TSV manufacturing and stacking process. One example is the effect of thermo-mechanical stress due to TSV fabrication process on the surrounding logic gates. In this dissertation, we analyze these effects and their consequences for delay testing. We provide quantitative results showing that the use of TSV-stress oblivious circuit models for test generation leads to considerable reduction in delay-test quality. We propose a test flow that uses TSV-stress aware circuit models to improve test quality.Another example of 3D-specific test challenge is the testability of TSVs. In this dissertation, we focus on TSV test prior to die bonding, as access to TSVs is limited at this stage. We propose a non-invasive method for pre-bond TSV test that does iv not require TSV probing. The method uses ring oscillators and duty-cycle detectors in order to detect variations in propagation delay of gates connected to a single-sided TSV. Based on the measured variations, we can diagnose the TSV and predict the size of resistive-open and leakage faults using a regression model based on artificial neural networks. In addition, we exploit different voltage levels to increase the robustness of the test method.In order to efficiently deliver test content to structures under test in a 3D stack, 3D design-for-test (DfT) architectures are needed. In this dissertation, we discuss existing 3D-DfT architectures and their optimization. We propose an optimization approach that takes uncertainties in input parameters into account and provides a solution that is efficient in the presence of input-parameter variations and minimizes test time, therefore reducing test cost.Post-silicon debug is a major challenge due to continuously increasing design complexity. Traditional debug methods using signal tracing suffer from the limited capacity of on-chip trace buffers that only allow for signal observation during a short time window. This dissertation proposes a low-cost debug architecture for massive signal tracing in 3D-stacked ICs with wide-I/O DRAM dies. The key idea is to use available on-chip DRAM for trace-data storage, which results in a significant increase of the observation window compared to traditional methods that use trace buffers. ...

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“…However, the fabrication process of TSV occasionally causes defects related to their conductor and insulator, e.g., voids and pin-holes [1][2][3] A void increases the resistance of the corresponding TSV and a pin-hole reduces the resistance between the corresponding TSV and the substrate [3][4][5]. These defects cause variations in the resistance and equivalent capacitance of TSVs those can be modeled as a propagation delay fault [4].…”

Section: Introductionmentioning

confidence: 99%

Efficient Pre-Bond Testing of TSV Defects Based on IEEE std. 1500 Wrapper Cells

Jung¹,

Ansari²,

Kim³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The yield of 3D stacked IC manufacturing improves with the pre-bond integrity testing of through silicon vias (TSVs). In this paper, an efficient pre-bond test method is presented based on IEEE std. 1500, which can precisely diagnose any happening of TSV defects. The IEEE std. 1500 wrapper cells are augmented for the proposed method. The pre-bond TSV test can be performed by adjusting the driving strength of TSV drivers and the test clock frequency. The experimental results show the advantages of the proposed approach.

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Filling TSV of different dimension using galvanic copper deposition

Cited by 7 publications

References 25 publications

The Limitation and Optimization of Bottom-Up Growth Mode in Through Silicon Via Electroplating

The Limitation and Optimization of Bottom-Up Growth Mode in Through Silicon Via Electroplating

Test and debug solutions for 3D-stacked integrated circuits

Efficient Pre-Bond Testing of TSV Defects Based on IEEE std. 1500 Wrapper Cells

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