Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations

Devos, Harald; Beyls, Kristof; Christiaens, Mark; Campenhout, Jan Van; D’Hollander, Erik H.; Stroobandt, Dirk

doi:10.1007/978-3-540-71528-3_11

Cited by 13 publications

(11 citation statements)

References 27 publications

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“…It has been semi-automatically generated using the design flow shown in Fig. 6 as described in [9] and summarized in this paragraph. A software implementation in C is split into statement definitions and the loop control structure.…”

Section: Case Study: System Integration Of An Idwtmentioning

confidence: 99%

Constructing Application-Specific Memory Hierarchies on FPGAs

Devos

Campenhout

Verbauwhede

et al. 2011

Transactions on High-Performance Embedded Architectures and Compilers III

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Abstract. The high performance potential of an FPGA is not fully exploited if a design suffers a memory bottleneck. Therefore, a memory hierarchy is needed to reuse data in on-chip buffer memories and minimize the number of accesses to off-chip memory. Buffer memories not only hide the external memory latency, but can also be used to remap data and augment the on-chip bandwidth through parallel access of multiple buffers. This paper discusses the differences and similarities of memory hierarchies on processor-and on FPGA-based systems and presents a step-by-step methodology to construct a memory hierarchy on an FPGA.

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Section: Case Study: System Integration Of An Idwtmentioning

confidence: 99%

Constructing Application-Specific Memory Hierarchies on FPGAs

Devos

Campenhout

Verbauwhede

et al. 2011

Transactions on High-Performance Embedded Architectures and Compilers III

Self Cite

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“…However, the polytope model [10] is able to expose the loop level parallelism of sequential loop-based programs by providing an abstraction to represent loop computations of an input specification as integer points inside of a polyhedron. As a result, the polytope model could be used for the synthesis of hardware architectures exploiting the LLP in digital signal processing algorithms in the form of highly-pipelined mono-processors [15] or processor arrays [16,17]. Processor arrays are regular, locally connected and massively parallel architectures with simple processing elements (PEs), whose structure is well suited for their implementation into FPGAs.…”

Section: Introductionmentioning

confidence: 99%

Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs

Perez-Andrade

Torres-Huitzil

Cumplido

2015

Microprocessors and Microsystems

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“…One of the representations used for HLS is the polytope model [6], which provides an abstraction to represent loop computations of an input specification as integer points inside of a polyhedron. As a result, the polytope model could be used for the synthesis of hardware architectures exploiting the LLP in digital signal processing algorithms in the form of processor arrays [7,8], or highly-pipelined monoprocessors [9].…”

Section: Introductionmentioning

confidence: 99%

Processor arrays generation for matrix algorithms used in embedded platforms

Perez-Andrade

Torres-Huitzil

Cumplido

et al. 2013

2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)

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Matrix algorithms are an important part of many digital signal processing applications as they are core kernels that usually need to be applied many times. Hardware assisted implementations using FPGAs provide a good compromise between performance, cost and power consumption. This paper presents a high level synthesis approach to generate embedded processor arrays for matrix algorithms based on the polytope model. The proposed approach provides a solution for efficient data memory accesses and data transferring for feeding the processor array, as well as it provides support for solving a set of problem size depending on FPGA available resources. The proposed approach has been validated by generating processor arrays for two case studies targeted for a Spartan-6 device. Results show that the implemented array outperforms hardware and software implementations targeted to embedded platforms as well.

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Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations

Cited by 13 publications

References 27 publications

Constructing Application-Specific Memory Hierarchies on FPGAs

Constructing Application-Specific Memory Hierarchies on FPGAs

Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs

Processor arrays generation for matrix algorithms used in embedded platforms

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