Finding double Euler trails of planar graphs in linear time [CMOS VLSI circuit design]

Abstract

This paper answers an open question in the design of complimentary metal-oxide semiconductor (CMOS) VLSI circuits. It asks whether a polynomial-time algorithm candecide if a given planar graph has a plane embedding E such that E has an Euler trail P = e 1 e 2 : : : e m and its dual graph has an Euler trail P = e 1 e 2 : : : e m where e i is the dual edge of e i for i = 1 ; 2; : : : ; m . This paper answers this question in the affirmative, by presenting a linear-time algorithm.