Fine-grained application source code profiling for ASIP design

Abstract

Current Application Specific Instruction set Processor (ASIP) design methodologies are mostly based on iterative architecture exploration that uses Architecture Description Languages (ADLs) and retargetable software development tools. However, for improved design efficiency, additional pre-architecture exploration tools are required to help narrow-down the huge design space and making coarsegrained Instruction Set Architecture (ISA) decisions before detailed ADL modeling. Extensive application code profiling is the key in such early design stages. Based on a novel code instrumentation technology, we present a microprofiling approach that fills the current gap between sourcelevel and instruction-level profilers and combines their advantages w.r.t. speed and accuracy. We show how the microprofiler is embedded into an advanced ASIP design flow and justify its use in a case study to design an MP3 decoder ASIP.

An Efficient Application Specific Memory Storage and ASIP Behavior Optimization in Embedded System

“…Greedy cycles from the state diagram we can determine optimal latency cycles which result in the MAL. There are infinitely many latencies cycles, one can from state diagram, suppose that (1,12), (1,4,6,8,10,12), (4,6), (4,6,8)…… are legitimate cycles traced from the state diagram. As simple cycles are latency cycles in which each state appear only ones.…”

“…Profiler have used to analyze the target source programs by collecting information on their execution based due to their data granularity scheme [10]. Profiler implements Preallocation of memory architecture and implements the execution time of application.…”

“…Profiler implements Preallocation of memory architecture and implements the execution time of application. A memory profiler used which implements dynamic profiling techniques to generate memory traces [10]. Memory object is computed load/store information for ASIP design mechanism.…”

“…The heterogeneous vector width method use to expose the heterogeneous vector widths for VLIW ASIP [10,13]. Effective automation is analyzed for VLIW ASIPs.…”

How sensitive is processor customization to the workload's input datasets?

“…LISATek is an example framework for generating custom processor instructions [11]. Several customizable architectures enable both instruction-set and microarchitecture customization.…”