Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs

Koch, Dirk; Beckhoff, Christian; Torrison, Jim

doi:10.1109/fccm.2010.19

Cited by 14 publications

(9 citation statements)

References 4 publications

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“…New tools such as ReCoBus Builder [Koch et al 2010] or RapidSmith [Lavin et al 2010] seem interesting and promising to provide efficient solutions to leverage these issues.…”

Section: The Generic Hardware Threadmentioning

confidence: 99%

Enhancing Reconfigurable Platforms Programmability for Synchronous Data-Flow Applications

Gantel

Khiar

Miramond

et al. 2012

ACM Trans. Reconfigurable Technol. Syst.

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Recent FPGAs allow the design of efficient and complex Heterogeneous Systems-on-Chip (HSoC). Namely, these systems are composed of several processors, hardware accelerators as well as communication media between all these components. Performances provided by HSoCs make them really interesting for data-flow applications, especially image processing applications. The use of this kind of architecture provides good performances but the drawback is an increase of the programming complexity.This complexity is due to the heterogeneous deployment of the application on the platform. Some functions are implemented in software to run on a processor, whereas other functions are implemented in hardware to run in a reconfigurable partition of the FPGA. This article aims to define a programming model based on the Synchronous Data-Flow model, in order to abstract the heterogeneity of the implementation and to leverage the communication issue between software and hardware actors.

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“…New tools such as ReCoBus Builder [Koch et al 2010] or RapidSmith [Lavin et al 2010] seem interesting and promising to provide efficient solutions to leverage these issues.…”

Section: The Generic Hardware Threadmentioning

confidence: 99%

Enhancing Reconfigurable Platforms Programmability for Synchronous Data-Flow Applications

Gantel

Khiar

Miramond

et al. 2012

ACM Trans. Reconfigurable Technol. Syst.

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“…Related studies such as online placement [5][6][7] attracted research interest in the past few years. But the increasing heterogeneous blocks and uneven routing in modern devices make these approaches very difficult to implement in reality and keep up with the times [16]. As a consequence, we feel it more meaningful and effective to address the challenges of DPR in the vendor-supported tool flows by developing algorithms to aid designers who are not architecture experts.…”

Section: Previous Workmentioning

confidence: 99%

Isba

Zhao

et al. 2012

Proceedings of the International Conference on Computer-Aided Design

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Dynamic Partial Reconfiguration (DPR) on FPGAs has attracted significant research interests in recent years since it provides benefits such as reduced area and flexible functionality. However, due to the lack of supporting synthesis tools in current DPR design flow, leveraging these benefits requires specific designer expertise with laborious manual design effort. Considering the complicated concurrency relations among functions, it is challenging to properly select Partial Reconfiguration Modules (PR Modules) and partition them into groups so that the hardware modules can be swapped in and out during the run time. What's more, the design of PR Modules also impacts reconfiguration latency and resource utilization greatly. In this paper, we formulate the PR Module generation problem into a standard Maximum-Weight Independent Set Problem (MWISP) so that the original manual exploration can be solved optimally and automatically. Our proposed algorithm not only supports various design constraints, but also has the ability to consider multiple objectives such as area and reconfiguration delay. Experimental results show that our approach can optimize resource utilization and reduce reconfiguration delay with good scalability. Especially, the implementation of the real design case shows that our approach can be embedded in the Xilinx's DPR design flow successfully and it can save around 70% reconfiguration latency overhead compared with the heuristic PR Module generation approaches.

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“…For efficiency and reliability reasons, we applied the ReCoBus-Builder tool flow approach (see [14], [15], and [16]) in our implementation. It supports the design of dynamically partially reconfigurable systems, especially the synthesis of communication hard-macros, floor-planing and generation of partial modules.…”

Section: Methodsmentioning

confidence: 99%

Bitonic Sorting on Dynamically Reconfigurable Architectures

Angermeier

Sibirko

Wanka

et al. 2011

2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PHD Forum

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Sorting is one of the most investigated tasks computers are used for. Up to now, not much research has been put into increasing the flexibility and performance of sorting applications by applying reconfigurable computer systems. There are parallel sorting algorithms (sorting circuits) which are highly suitable for VLSI hardware realization and which outperform sequential sorting methods applied on traditional software processors by far. But usually they require a large area that increases with the number of keys to be sorted. This drawback concerns ASIC and statically reconfigurable systems.In this paper, we present a way to adopt the well-known Bitonic sorting method to dynamically reconfigurable systems such that this drawback is overcome. We present a detailed description of the design and actual implementation, and we present experimental results of our approach to show its benefits in performance and the trade-offs of our approach.

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Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs

Cited by 14 publications

References 4 publications

Enhancing Reconfigurable Platforms Programmability for Synchronous Data-Flow Applications

Enhancing Reconfigurable Platforms Programmability for Synchronous Data-Flow Applications

Isba

Bitonic Sorting on Dynamically Reconfigurable Architectures

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