Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop

Abstract

An area-efficient non-volatile flip flop (NVFF) is proposed. Two minimum-sized Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and two magnetic tunnel junction (MTJ) devices are added on top of a conventional D flip-flop for temporary storage during the power-down. An area overhead of the temporary storage is minimized by reusing a part of the D flip-flop and an energy overhead is reduced by a current-reuse technique. In addition, two optimization strategies of the use of the proposed NVFF are proposed: (1) A module-based placement in a design phase for minimizing the area overhead; and (2) a dynamic write pulse modulation at runtime for reducing the energy overhead. We evaluated the proposed NVFF circuit using a compact MTJ model targeting an implementation in a 10 nm technology node. Results indicate that area overhead is 6.9 % normalized to the conventional flip flop. Compared to the best previously known NVFFs, the proposed circuit succeeded in reducing the area by 4.1 × and the energy by 1.5 × . The proposed placement strategy of the NVFF shows an improvement of nearly a factor of 2–18 in terms of area and energy, and the pulse duration modulation provides a further energy reduction depending on fault tolerance of programs.

Neuromorphic Computing Using Emerging Synaptic Devices: A Retrospective Summary and an Outlook

“…This review introduces an implementation of the approximate computing using a synaptic device. Specifically, an approximate flip-flop using MTJ devices is reviewed [77]. The flip-flop is is a hybrid version of the conventional D flip-flop (D-FF) and non-volatile storage using MTJs for fine-grained power gating.…”

“…If we can control error probability of each flop individually, we then would reduce energy effectively. In [77], the error rate of the flip-flop is easily controlled by changing pulse duration of a control node. Figure 13 shows a schematic view of the flip-flop and an inverse relation between the error rate and energy consumption.…”

Hybrid Non-Volatile Flip-Flops Using Spin-Orbit-Torque (SOT) Magnetic Tunnel Junction Devices for High Integration and Low Energy Power-Gating Applications

“…Non-volatile flip-flops (NVFFs) are promising enablers of fine-grained power gating techniques because these circuits do not require a complex interface to transfer data from/to the external storage (e.g., SRAM) before powering down [1][2][3][4][5][6]. The NVFFs can sustain data without power supply.…”

Editorial for the Special Issue on Emerging Memory and Computing Devices in the Era of Intelligent Machines

“…In "Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop", J. Park and Y. Yim [3] explore some of the advantages of MRAM in terms of power management, by taking advantage of its nonvolatility to enable a flip-flop that retains its information without applied voltage. (ii) There are also several examples of RRAM and phase-change memories discussed throughout the selected articles.…”