FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

Hisamoto, D.; Lee, Wen‐Chin; Kedzierski, J.; Takeuchi, Hideki; Asano, K.; Kuo, C.; Anderson, Erik H.; King, Tsu‐Jae; Bokor, Jeffrey; Hu, Chenming

doi:10.1109/16.887014

Cited by 1,375 publications

(111 citation statements)

References 10 publications

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“…Gate assisted Kelvin test structure to measure the electron and hole flows at the same nanowire contacts Hui Yuan, 1,2,a) Ahmad Badwan, 1 Curt A. Richter, 2 Hao Zhu, 1,2 Oleg Kirillov, 2 Dimitris E. Ioannou, 1 A gate assisted Kelvin test structure based on Si nanowire field effect transistors has been designed and fabricated for the characterization of the transistor source/drain contacts. Because the Si nanowire field effect transistors exhibit ambipolar characteristics with electron current slightly lower than the hole current, we can select the type of carriers (electrons or holes) flowing through the same contacts and adjust the current by the applied gate voltage.…”

mentioning

confidence: 99%

Gate assisted Kelvin test structure to measure the electron and hole flows at the same nanowire contacts

Yuan

Badwan

Richter

et al. 2014

Applied Physics Letters

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A gate assisted Kelvin test structure based on Si nanowire field effect transistors has been designed and fabricated for the characterization of the transistor source/drain contacts. Because the Si nanowire field effect transistors exhibit ambipolar characteristics with electron current slightly lower than the hole current, we can select the type of carriers (electrons or holes) flowing through the same contacts and adjust the current by the applied gate voltage. In this way, we are able to measure the characteristics of the same contact with either pure electron or hole flow. In addition, we found that the nanowire contacts behave very differently depending on the current flow directions. This indicates that the source and drain contact resistance can be dramatically different. Such a gate assisted Kelvin Test structure will lead to future metrology and applications in nanoelectronics.

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mentioning

confidence: 99%

Gate assisted Kelvin test structure to measure the electron and hole flows at the same nanowire contacts

Yuan

Badwan

Richter

et al. 2014

Applied Physics Letters

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“…For FinFET, the body thickness T Fin should be approximately half of the gate length L G to provide better control of short channel effects. When the L G /T FIN ratio is smaller than 1.5, the drain induced barrier lowering, subthreshold swing, and leakage current are increased sensibly [2][3][4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

“…SOI (Silicon-on-insulator) wafers are typically used for Fin-FET fabrication [9]. The use of SOI substrate in manufacturing microprocessors has been introduced by major semiconductor companies with the aim to minimize parasitic capacitances and improve current drive, circuit speed, and power consumption [1].…”

Section: Introductionmentioning

confidence: 99%

Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor

Boukortt¹,

Hadri²,

Caddemi³

et al. 2016

Transactions on Electrical and Electronic Materials

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In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator ATLAS™ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/ off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.

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“…1(a) shows the 3D structure of a self aligned triple-gate FinFET with raised source/drain (RSD) along the source-drain direction [3,4]. Compared to the conventional planer processes, there is an additional coupling capacitance between gate and RSD.…”

Section: Introductionmentioning

confidence: 99%

Structure optimization for timing in nano scale FinFET

Kanamoto

Akamine

Ammo

et al. 2015

IEICE Electron. Express

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This paper suggests a methodology to model and optimize parasitic capacitance and resistance on nano-scale FinFET devices in terms of timing. We suggest to optimize the gate spacer thickness to minimize signal propagation delay. Due to its own 3D construction, FinFET accompanies large parasitic resistance (R) and capacitance (C) elements. It brings the larger signal delay impact on the parasitic compared to the conventional planer MOS FET devices. We reveal that the spacer thickness dependence of the RC elements results in a minimal value in the signal propagation delay. The experimental results show that the signal propagation delay can be improved up to 10% in 16 nm era FinFET circuits with controlling the spacer thickness.

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FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

Cited by 1,375 publications

References 10 publications

Gate assisted Kelvin test structure to measure the electron and hole flows at the same nanowire contacts

Gate assisted Kelvin test structure to measure the electron and hole flows at the same nanowire contacts

Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor

Structure optimization for timing in nano scale FinFET

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