Finite element analysis of lead-free drop test boards

Marjamäki, Pekka; Mattila, Toni T.; Kivilahti, J.K.

doi:10.1109/ectc.2005.1441306

Cited by 18 publications

(13 citation statements)

References 6 publications

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“…All failures occurred in the joints which were reflowed twice (top PCB regions). This phenomenon agrees with mechanical simulations, which indicated that the stress during the drop impact test is greater on the component side [23]. Also, the additional reflow process to interconnect the top PCB to the bottom PCB increased the IMC thickness on the top PCB region in all samples.…”

Section: Drop Impact Reliability Of As-assembled Solder Jointssupporting

confidence: 88%

An eco-friendly Cu-Zn wetting layer for highly reliable solder joints

Kim

2013

2013 IEEE 63rd Electronic Components and Technology Conference

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Section: Drop Impact Reliability Of As-assembled Solder Jointssupporting

confidence: 88%

An eco-friendly Cu-Zn wetting layer for highly reliable solder joints

Kim

2013

2013 IEEE 63rd Electronic Components and Technology Conference

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“…This asymmetric loading effect is reinforced by the strain-rate hardening of the leadfree bulk solder during shock loading. The results of the FEmodelling of the solder interconnections point out that in drop tests the tensile stresses at the component side interfacial region are much larger than those on the PWB due to the reasons mentioned above [16] . Hence, it is understandable that the component side reaction layers are more vulnerable to brittle cracking even in such a case, shown in Fig Depending on the components UBM the reaction zone can be composed of one or more of the following phases: Cu 6 Sn 5 , (Cu,Ni) 6 Sn 5 , (Ni,Cu) 3 Sn 4 , Ag 3 Sn or of the ternary NiSnP layer.…”

Section: Effect Of Printed Wiring Board Protective Coatingsmentioning

confidence: 97%

Drop test reliability of wafer level chip scale packages

Alajoki¹,

Nguyen²,

Kivilahti³

Proceedings Electronic Components and Technology, 2005. ECTC '05.

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The reliability of the two different types of WL-CSP components being reflow-soldered with a near eutectic Sn3.8Ag0.7Cu and eutectic SnPb solder pastes on Ni(P)/Auand OSP-coated multilayer printed wiring boards have been investigated by employing the standard drop test, statistical failure analyses, fractography and microstructural characterization methods. A significant difference in the reliability performance of the components was observed: the components with the (Al)Ni(V)/Cu metallization (UBM) were more reliable than those with the electroless Ni(P)/Au metallization -independently of the bump, solder paste, surface finish materials or the pad structure of the boards used. The failure analyses revealed that the primary failure mode in the component side is the cracking of interconnections along a brittle NiSnP layer between the electroless Ni(P) of high P-content and the solder alloy, while components with (Al)Ni(V)/Cu UBM fail by cracking along the [Cu,Ni]6Sn5 intermetallic layer. On the board side the cracking occurs in the porous NiSnP layer formed between the electroless Ni(P) metallization and the (Cu,Ni) 6 Sn 5 intermetallic layer. The fact that the cracking occurs predominantly at the components side reaction layer is due to three factors: higher normal stresses in the component side, brittleness of the reaction layer(s) and the strain-rate hardening of the bulk solder interconnections. It is to be noted that the primary failure mode differs from that typically observed in thermally cycled test assemblies, where the nucleation and propagation of cracks are strongly enhanced by the recrystallization of the solder inter-connections.

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“…This sampling rate of the system provides 50 sample points per millisecond for each component (50,000 per second), so that several samples are taken during the initial shock pulse (as short as 0.3 ms for 2900G). The primary deflection time of the board and first harmonic vibration frequency in a 1500G drop are near 4 ms and 240Hz [20]; with a 50Khz sampling frequency this system provides more than 200 samples per board deflection cycle. During each drop the ADC records every data point taken from the fifteen components and supply voltage and saves a data file for later analysis.…”

Section: Failure Detection Systemsmentioning

confidence: 99%

Drop test reliability of lead-free chip scale packages

Farris

Pan

Liddicoat

et al. 2008

2008 58th Electronic Components and Technology Conference

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This paper presents the drop test reliability of 0.5mm pitch lead-free chip scale packages (CSPs). Fifteen 0.5mm pitch CSPs were assembled on a standard JEDEC drop reliability test board with Sn3.0Ag0.5Cu lead-free solder. Eight boards were edge-bonded with a UV-cured acrylic; eight boards were edgebonded with a thermal-cured epoxy; and twelve boards were assembled without edge bonding. Half of the edge-bonded test boards were subjected to drop tests at a peak acceleration of 1500G with a pulse duration of 0.5ms, and the other half subjected to drop tests at a peak acceleration of 2900G with a pulse duration of 0.3ms. Half of the test boards without edge bonding were subjected to drop tests at a peak acceleration of 900G with a pulse duration of 0.7ms, and the other half subjected to drop tests at a peak acceleration of 1500G with a pulse duration of 0.5ms. Two drop test failure detection systems were used in this study to monitor the failure of solder joints: a high-speed resistance measurement system and a post-drop static resistance measurement system. The high-speed resistance measurement system, which has a scan frequency of 50KHz and a 16-bit signal width, is able to detect intermittent failures during the short drop impact duration. Statistics of the number of drops to failure for the 15 component locations on each test board are reported. The effect of component position on drop test reliability is discussed. The test results show that the drop test performance of edge-bonded CSPs is five to eight times better than the CSPs without edge bonding. However, the drop test reliability of edge-bonded CSPs with the thermal-cured epoxy is different from that with edge-bonded CSPs with the UV-cured acrylic. The solder crack location and crack area are characterized with the dye penetrant method. The fracture surfaces are studied using scanning electron microscopy (SEM).

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Finite element analysis of lead-free drop test boards

Cited by 18 publications

References 6 publications

An eco-friendly Cu-Zn wetting layer for highly reliable solder joints

An eco-friendly Cu-Zn wetting layer for highly reliable solder joints

Drop test reliability of wafer level chip scale packages

Drop test reliability of lead-free chip scale packages

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