FIR filter design based on retiming automation using VLSI design metrics

Yagain, Deepa; Vijaya, Krishna A.

doi:10.1109/time-e.2013.6611956

Cited by 7 publications

(6 citation statements)

References 14 publications

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“…The FIR and IIR filters are designed with respect to different adders and multipliers combinations. As an application example, IIR and FIR filters [25] of order 10 are considered. Table 5 shows the results of FIR/IIR filters before and after retiming for particular adder and multiplier combinations.…”

Section: Area Power and Timing Results For Digital Filter Before Anmentioning

confidence: 99%

Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Yagain

Krishna

2014

VLSI Design

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Retiming is a transformation which can be applied to digital filter blocks that can increase the clock frequency. This transformation requires computation of critical path and shortest path at various stages. In literature, this problem is addressed at multiple points. However, very little attention is given to path solver blocks in retiming transformation algorithm which takes up most of the computation time. In this paper, we address the problem of optimizing the speed of path solvers in retiming transformation by introducing high level synthesis of path solver algorithm architectures on FPGA and a computer aided design tool. Filters have their combination blocks as adders, multipliers, and delay elements. Avoiding costly multipliers is very much needed for filter hardware implementation. This can be achieved efficiently by using multiplierless MCM technique. In the present work, retiming which is a high level synthesis optimization method is combined with multiplierless filter implementations using MCM algorithm. It is seen that retiming multiplierless designs gives better performance in terms of operating frequency. This paper also compares various retiming techniques for multiplierless digital filter design with respect to VLSI performance metrics such as area, speed, and power.

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Section: Area Power and Timing Results For Digital Filter Before Anmentioning

confidence: 99%

Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Yagain

Krishna

2014

VLSI Design

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“…In [9], an effective implementation of FIR filters with high-speed adders was presented for signalprocessing applications. In [7], the register minimization retiming technique was used to design an effective filter. The design of low-complexity FIR filters has been the focus of active study over the past 20 years.…”

Section: Related Workmentioning

confidence: 99%

“…However, FIR filters are frequently used in the design of digital filters due to their linear phase and stability [5]. FIR filters can be implemented as specialized hardware, such as Application-Specific Integrated Circuits (ASICs) [6][7]. A digital filter with an FIR is one whose impulse response has a finite duration and settles to zero in a finite amount of time.…”

Section: Introductionmentioning

confidence: 99%

Implementation of a Finite Impulse Response Filter using PUFs to Avoid Trojans

Bukke,

Manjunathachari,

Sabbavarapu

2023

Eng. Technol. Appl. Sci. Res.

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In the modern era of signal processing, digital filters play an important role in real-time applications such as communication, consumer electronics, digital signal processing, audio, etc. In digital filter design, Finite Impulse Response (FIR) filters are highly preferable due to their linear phase and inherent stability. These filters benefit from being time-invariant and simple to implement with minimal computational requirements. Therefore, the hardware security of FIR filters is essential for good performance and reliable results. On the other hand, there is the possibility of hardware threats, such as tampering, reverse engineering, hardware Trojans, etc., as the design of an FIR filter involves many stages. Such hardware attacks on FIR filters can cause several problems, including performance degradation, leakage of confidential information, lack of stability, etc. This study presents the design and implementation of a Trojan-aware FIR filter using Physical Unclonable Functions (PUFs). The key feature of PUFs is that they generate a unique and unpredictable response for each given challenge. In the proposed design, PUFs were used to generate the FIR filter coefficients that are unique and unpredictable by attackers/trojans to improve security. The security of FIR with PUF was tested using ML-based challenges, and the results showed approximately 30% more reliability and consistency compared to the FIR without PUFs.

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“…Retiming approach optimizes the hardware required for the design (Awasthi and Raj, 2014) with the help of relocating the delay elements. Retimed filters (Yagain and Vijaya, 2013) are realized with suitable specifications and register minimization which improves the performance metrics of the design. Retimed data flow graphs (Parhi, 2008) help to identify the signal flow and to optimize the parameters.…”

Section: Introductionmentioning

confidence: 99%

Decisive structures for multirate FIR filter incorporating retiming and pipelining schemes

Mariammal

Banu

Pari

et al. 2020

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Purpose Very large-scale integration (VLSI) digital signal processing became very popular and is predominantly used in several emerging applications. The optimal design of multirate filter with improvement in performance parameters such as less area, high speed and less power is the challenging task in most of the signal processing applications. This study aims to propose several effective multirate filter structures to accomplish sampling rate conversion. Design/methodology/approach The multirate filter structures considered in this work are polyphase filter and coefficient symmetry-based finite impulse response filter. The symmetry scheme particularly brings down the complexity to significant extent. To bring improvement in speed, delay registers are inserted at appropriate path with the help of pipelining and retiming scheme. Findings In this paper, the three tasks have been considered. First, the polyphase coefficient symmetry and modified polyphase (MP) structure is designed. Second, the pipelining is applied to the polyphase structure and the obtained results are compared with the polyphase structure. In third, retiming is applied to the polyphase structure and the performance comparison is carried out. The structures are realized for various orders, and the comparative analysis is carried out with the filter order N = 12, 30, 42, 8, 11 and 24 and the results are stated. The performance of all the accomplished structures is analyzed using Altera Quartus with the family cyclone II, device EP2C70F672C6. The results show that the multirate filter using pipelining and retiming offers better performance when examining with the conventional structures. Retimed and pipelined MP structure achieves a speed enhancement of about 33.81% when examining with the conventional polyphase (CP) structure with retiming and pipelining for N = 24 and M = 5. Likewise, the 2/3 structure of pipelined coefficient symmetry approach offers area reduction of about 54.76% over 2/3 structure of pipelined polyphase approach for N = 30 with little reduction in power. The fine grain pipelined and retimed MP structure with N = 11 and M = 3 avails critical path delay reduction of about 28.15% when examining with the corresponding fine grain pipelined and retimed CP structure. Originality/value The proposed distinct structures offer better alternative to conventional structures because of the symmetric coefficients, performance enhancement using pipelining and retiming based rate conversion structures. The suggested structures can be used for achieving different rates in software radios.

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FIR filter design based on retiming automation using VLSI design metrics

Cited by 7 publications

References 14 publications

Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Implementation of a Finite Impulse Response Filter using PUFs to Avoid Trojans

Decisive structures for multirate FIR filter incorporating retiming and pipelining schemes

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