First demonstration of monocrystalline silicon macaroni channel for 3-D NAND memory devices

Delhougne, Romain; Arreghini, A.; Rosseel, Erik; Hikavyy, Andriy; Vecchio, E.; Zhang, L.; Pak, M.; Nyns, L.; Raymaekers, Tom; Jossart, N.; Breuil, L.; V-Palayam, S. S.; Tan, Chi Lim; bosch, G. Van den; Furnemont, A.

doi:10.1109/vlsit.2018.8510635

Cited by 10 publications

(4 citation statements)

References 1 publication

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“…However, after the filler formation, the amorphous Si liner was recessed and replaced by epitaxially grown Si. Following that, the drain was formed in the same way as in the case of MC-POLY [9]. After the channel and drain formation, all four types of the devices went through staircase patterning and contact formation.…”

Section: A Samplesmentioning

confidence: 99%

Impact of Mechanical Stress on 3-D NAND Flash Current Conduction

Kruv

Arreghini

Verreck

et al. 2020

IEEE Trans. Electron Devices

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This work experimentally investigates current conduction in 3-D NAND under up to 7 GPa of externally applied compressive mechanical stress. The impact of channel crystallinity and geometry is studied by comparing four types of Si channels: polycrystalline full channel, single-crystal full channel, polycrystalline macaroni channel, and single-crystal macaroni channel. In the studied channel types, the mechanical stress was found to cause reversible degradation of I ON (up to one order of magnitude) and I OFF (up to seven orders of magnitude). Using TCAD simulations, I ON and I OFF deterioration are attributed to carrier mobility and Si bandgap decreases under mechanical stress, respectively. The simulations also suggest that both effects depend on the channel morphology, which results in a different extent of stress impact on the four studied types of Si channels.

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Section: A Samplesmentioning

confidence: 99%

Impact of Mechanical Stress on 3-D NAND Flash Current Conduction

Kruv

Arreghini

Verreck

et al. 2020

IEEE Trans. Electron Devices

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“…Among them, the most relevant are likely those coming from the polycrystalline nature of the silicon channel in the vertical NAND strings. In fact, even though possible process flows resulting in monocrystalline silicon have been recently proposed [73], at the present time all the integration schemes for 3-D arrays adopted by major semiconductor manufacturers give rise only to a polysilicon channel for the strings. Many drawbacks arise from that and set future challenges for the technology, mainly related to the presence and the haphazardness in the configuration of the polysilicon grain boundaries.…”

Section: Reliability Issues Specific To 3-d Arraysmentioning

confidence: 99%

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Compagnoni

Spinelli

2019

IEEE Trans. Electron Devices

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This paper reviews what changed in the reliability of NAND Flash memory arrays after the paradigm shift in technology evolution determined by the transition from 2-D to 3-D integration schemes. Starting from a quick glance at the fundamentals of raw array reliability, the reasons for its worsening with the evolution of 2-D technologies will be discussed, focusing on the physical phenomena which contributed more to that outcome. By exploring the dependence of the magnitude of these phenomena on cell and array parameters, the abrupt improvements achieved from the 3-D transition in terms of raw array reliability will then be explained, highlighting also that these improvements were turned into new opportunities for the technology. Finally, the physical issues specific to 3-D arrays will be addressed, providing a glimpse of the challenges that the NAND Flash technology will have to face from the standpoint of array reliability in the near future. Index Terms-3-D NAND Flash arrays, Flash memories, semiconductor device modeling, semiconductor device reliability. I. INTRODUCTIONT HE NAND Flash technology has become, today, the undisputed leader in the nonvolatile memory market, largely overcoming the hard-disk drive (HDD) technology in terms of revenues [1]. This outcome has been determined by the capability of the NAND Flash solution to address quite a variety of applications better than any other storage technology, thanks to successful tradeoffs among cost, performance, and reliability. At the heart of all that there is, of course, the possibility to steadily increase the integration density of the NAND array and, in turn, the memory capacity per chip. This is clearly proved in Fig. 1 in terms of gross bit storage density (GBSD), i.e., the ratio between the storage capacity and the total chip area, of the NAND Flash chips presented at the IEEE International Solid-State Circuits Conference (IEEE ISSCC) since 2001 (see [2] for further details on the analysis methodology).Up to ∼2015, the GBSD increase was achieved, first of all, through a constant pace miniaturization of the memory cells

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“…[1][2][3][4] Vertically stacked NAND flash memory, or 3D NAND, [5][6][7] has replaced planar NAND by overcoming many issues in 2D NAND when scaling beyond 20 nm technology nodes, including the requirement of advanced lithography techniques, increased cell interference due to proximity effects, and more severe threshold voltage (V TH ) shift per electron injection. [8][9][10] However, 3D NAND also faces challenges during the z-direction scaling (i.e., stacking more layers), especially with the poly-Si channel. First, the mobility of the poly-Si in the flash memories is typically less than 10 cm 2 V −1 s −1 due to the disordered structure, [11] resulting in a low cell current and insufficient sense margin after stacking hundreds of layers.…”

Section: Introductionmentioning

confidence: 99%

Computational Associative Memory with Amorphous Metal‐Oxide Channel 3D NAND‐Compatible Floating‐Gate Transistors

Sun

Samanta

et al. 2022

Adv Elect Materials

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3D NAND has been enabling continuous NAND density and cost scaling beyond conventional 2D NAND since sub‐20‐nm nodes. However, its poly‐Si channel suffers from low mobility, instability caused by grain boundaries, and large device‐to‐device variations in electrical characteristics at highly scaled device dimensions. These drawbacks can be overcome by introducing an amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) channel, which has the advantages of ultralow OFF current, back‐end‐of‐line compatibility, higher mobility than poly‐Si, and free of grain boundaries due to the amorphous nature. In this work, ultrascaled floating‐gate (FG) transistors with a channel length down to 60 nm are reported, achieving the highest ON current of 127 µA µm−1 among all reported a‐IGZO‐based flash devices for high‐density, low‐power, and high‐performance 3D NAND applications. Furthermore, a nonvolatile and area‐efficient ternary content‐addressable memory (TCAM) with only two parallel‐connected a‐IGZO FG transistors is experimentally demonstrated to address the TCAM scalability issue. Experimentally calibrated array‐level simulations show that this design achieves at least a 240 × array‐size scalability and a 2.7‐fold reduction in search energy than TCAMs based on complementary metal‐oxide‐semiconductor technology using 16 transistors, two‐transistor‐two‐resistive random access memory, and two‐ferroelectric field‐effect‐transistor.

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First demonstration of monocrystalline silicon macaroni channel for 3-D NAND memory devices

Cited by 10 publications

References 1 publication

Impact of Mechanical Stress on 3-D NAND Flash Current Conduction

Impact of Mechanical Stress on 3-D NAND Flash Current Conduction

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Computational Associative Memory with Amorphous Metal‐Oxide Channel 3D NAND‐Compatible Floating‐Gate Transistors

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