First Demonstration of WSe&lt;inf&gt;2&lt;/inf&gt; Based CMOS-SRAM

Pang, Chin‐Sheng; Thakuria, Niharika; Gupta, Sumeet Kumar; Chen, Zhihong

doi:10.1109/iedm.2018.8614572

Cited by 25 publications

(18 citation statements)

References 10 publications

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“…Two-dimensional (2D) transitional metal dichalcogenides (TMDs) have attracted wide attention, owing to their excellent material properties and potential applications in post-CMOS, [1][2][3][4][5][6][7][8] neuromorphic computing, [9][10][11] as well as flexible electronics. [12][13][14][15] Studying semiconducting TMDs (e.g.…”

Section: Introductionmentioning

confidence: 99%

Atomically Controlled Tunable Doping in High‐Performance WSe₂ Devices

Pang

Hung

Khosravi

et al. 2020

Adv Elect Materials

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Two-dimensional transitional metal dichalcogenide (TMD) field-effect transistors (FETs) are promising candidates for future electronic applications, owing to their excellent transport properties and potential for ultimate device scaling. However, it is widely acknowledged that substantial contact resistance associated with the contact-TMD interface has impeded device performance to a large extent. It has been discovered that O2 plasma treatment can convert WSe2 into WO3-x and substantially improve contact resistances of p-type WSe2 devices by strong doping induced thinner depletion width. In this paper, we carefully study the temperature dependence of this conversion, demonstrating an oxidation process with a precise monolayer control at room temperature and multilayer conversion at elevated temperatures. Furthermore, the lateral oxidation of WSe2 under the contact revealed by HR-STEM leads to potential unpinning of the metal Fermi level and Schottky barrier lowering, resulting in lower contact resistances. The p-doping effect is attributed to the high electron affinity of the formed WO3-x layer on top of the remaining WSe2 channel, and the doping level is found to be 2 dependent on the WO3-x thickness that is controlled by the temperature. Comprehensive materials and electrical characterizations are presented, with a low contact resistance of ~528  m and record high on-state current of 320 A/m at -1V bias being reported.

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Section: Introductionmentioning

confidence: 99%

Atomically Controlled Tunable Doping in High‐Performance WSe₂ Devices

Pang

Hung

Khosravi

et al. 2020

Adv Elect Materials

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“…Hence, the ACS among the different technology scenarios has the best power efficiency with slightly worse speed than the FinFET + Cu counterpart. There are some works that show the good noise margin and low power of 2D-FET SRAM such as WSe 2 -based SRAM design [42]. However, the performance of the 2D-FET SRAM is around one order of magnitude smaller than the CNFET counterpart.…”

Section: B Comparisons With the Finfet Sram Baselinementioning

confidence: 99%

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part II: CNT Interconnect Optimization

Chen

Lin

Liang

et al. 2022

IEEE Trans. VLSI Syst.

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The size and parameter optimization for the 5-nm carbon nanotube field effect transistor (CNFET) static random access memory (SRAM) cell was presented in Part I of this article. Based on that work, we propose a carbon nanotube (CNT) SRAM array composed of the schematically optimized CNFET SRAM and CNT interconnects. We consider the interconnects inside the CNFET SRAM cell composed of metallic single-wall CNT (M-SWCNT) bundles to represent the metal layers 0 and 1 (M0 and M1). We investigate the layout structure of CNFET SRAM cell considering CNFET devices, M-SWCNT interconnects, and metal electrode Palladium with CNT (Pd-CNT) contacts. Two versions of cell layout designs are explored and compared in terms of performance, stability, and power efficiency. Furthermore, we implement a 16 Kbit SRAM array composed of the proposed CNFET SRAM cells, multiwall CNT (MWCNTs) inter-cell interconnects and Pd-CNT contacts. Such an array shows significant advantages, with the read and write overall energy-delay product (EDP), static power consumption, and core area of 0.28×,0.52×, and 0.76× respectively to 7-nm FinFET-SRAM array with copper interconnects, whereas the read and write static noise margins are 6% and 12% respectively larger than the FinFET counterpart.This work was supported in part by the European Commission H2020 CONNECT Project under Agreement 688612 (http://www.connect-h2020.eu/) and in part by the Marie Skłodowska-Curie Individual Fellowship under Grant 894805 (H-3D-SOC).

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“…We present a benchmark chart (Fig 5d) to compare the performance of our devices against flake and CVD 2D material FETs in literature 34,35,36,37,38,39,40,41,42,43 . We choose the peak of transconductance (gm,max) measured at VDS = 1 V and SSmin as the two metrics for comparison, similar to conventional Si transistors.…”

Section: Benchmark Projection and Conclusionmentioning

confidence: 99%

Impact of Device Scaling on the Electrical Properties of MoS2 Field-effect Transistors

Arutchelvan¹,

Smets²,

Verreck³

et al. 2021

Preprint

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Two-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with Silicon gate-all-around devices.

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First Demonstration of WSe<inf>2</inf> Based CMOS-SRAM

Cited by 25 publications

References 10 publications

Atomically Controlled Tunable Doping in High‐Performance WSe₂ Devices

Atomically Controlled Tunable Doping in High‐Performance WSe₂ Devices

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part II: CNT Interconnect Optimization

Impact of Device Scaling on the Electrical Properties of MoS2 Field-effect Transistors

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First Demonstration of WSe<inf>2</inf> Based CMOS-SRAM

Cited by 25 publications

References 10 publications

Atomically Controlled Tunable Doping in High‐Performance WSe2 Devices

Atomically Controlled Tunable Doping in High‐Performance WSe2 Devices

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part II: CNT Interconnect Optimization

Impact of Device Scaling on the Electrical Properties of MoS2&nbsp;Field-effect Transistors

Contact Info

Product

Resources

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Atomically Controlled Tunable Doping in High‐Performance WSe₂ Devices

Atomically Controlled Tunable Doping in High‐Performance WSe₂ Devices

Impact of Device Scaling on the Electrical Properties of MoS2 Field-effect Transistors