First results from the CIC data aggregation ASIC for the Phase 2 CMS Outer Tracker

Nodari, B.; Bergamin, G.; Caponetto, L.; Caratelli, A.; Ceresa, Davide; Clercq, J. De; Galbit, G.; Jain, Sandhya; Kloukinas, K.; Scarfì, S.; Viret, Sarah Seif El Nasr-Storey Sebastien

doi:10.22323/1.370.0102

Cited by 3 publications

(6 citation statements)

References 4 publications

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“…In order to validate the chip model, a first physical version, the CIC1, was developed and implemented, along with a complete standalone testbench. This chip, which incorporates all the data processing functionalities of the final system along with the same footprint, was successfully tested in 2019 [5]. These results paved the way for a fast second iteration in 2020 of the CIC2.…”

Section: Introductionmentioning

confidence: 92%

“…The main features of the CIC2 were already presented in [4,5]. The chip aggregates the data coming from 48 input lines at the rate of 320 MHz.…”

Section: Cicdesign Featuresmentioning

confidence: 99%

“…The CIC2 chip tests started in December 2019 using the same experimental setup as the CIC1 (both chips have the same footprint) [5]. Characterization tests described in this note were performed with CIC2 chips wirebonded on custom test carrier boards.…”

Section: Cic2 Standalone Test Setupmentioning

confidence: 99%

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CIC2: a radiation tolerant 65 nm data aggregation ASIC for the future CMS tracker

Viret¹,

Bergamin²,

Caponetto³

et al. 2022

J. Inst.

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The Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) and Strip-Strip (2S) modules of the future Phase-II CMS Outer Tracker upgrade at the High-Luminosity LHC (HL-LHC). This data aggregator, designed in 65 nm CMOS technology, will be a key element of the tracker front-end chain. A first prototype, CIC1, was tested successfully in early 2019 and was followed by the development of a final radiation tolerant version of the chip: the CIC2. CIC2 design, implementation, and complete test results, are presented.

show abstract

Section: Introductionmentioning

confidence: 92%

“…The main features of the CIC2 were already presented in [4,5]. The chip aggregates the data coming from 48 input lines at the rate of 320 MHz.…”

Section: Cicdesign Featuresmentioning

confidence: 99%

See 1 more Smart Citation

CIC2: a radiation tolerant 65 nm data aggregation ASIC for the future CMS tracker

Viret¹,

Bergamin²,

Caponetto³

et al. 2022

J. Inst.

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show abstract

“…In order to validate the chip model a first version (CIC1) was developed and implemented along with a complete standalone testbench. A second version (CIC2) [1] was submitted in 2020 based on an architecture that includes a 640 MHz clock tree, power optimization and triplication for radiation hardness. CIC2 has been tested and characterized during 2020 and it fulfills the CMS OT requirements.…”

Section: Introductionmentioning

confidence: 99%

CIC: a radiation tolerant 65 nm data aggregation ASIC for the future CMS tracking detector at LHC

et al. 2023

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For the Phase II upgrade at HL-LHC, CMS needs a new Outer Tracker detector able to cope with reduced material budget, increased radiation tolerance and higher pile-up conditions with respect to LHC. The main feature of the Outer Tracker will be its inclusion at the first level of the CMS trigger system with data readout at 40 MHz. Two types of modules, Pixel-Strip and Strip-Strip will equip the Outer Tracker. Each module consists of a superposition of two silicon layers, able to detect charged particles, and an innovative readout electronics, allowing a significant data rate reduction. The Concentrator Integrated Circuit (CIC) is a 65 nm CMOS radiation tolerant front-end ASIC for both modules. It is considered a fundamental element of the future detector front-end chain due to its role in aggregating and compressing data from 8 front-end ASICs on each module. It reduces the data throughput by an order of magnitude. Two first version of the CIC were previously developed and tested. This paper will present the pre-production version, called CIC2.1, together with the functional and wafer test results.

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“…The Macro-Pixel ASICs (MPA) [9] are bump-bonded to the former, while the latter is wire-bonded to a hybrid and is read out by the Short Strip ASIC (SSA) [10,11] bump-bonded to the same hybrid. A module is read out by sixteen SSAs and MPAs, with a pair of Concentrator Integrated Circuits (CICs) [12] responsible for aggregating their returned data. The Low-power Gigabit Transceiver (LpGBT) [13] distributes clock, trigger and control signals to the eight SSAs and eight MPAs on each side of the module.…”

Section: Introductionmentioning

confidence: 99%

Beam test performance of a prototype module with Short Strip ASICs for the CMS HL-LHC tracker upgrade

et al. 2022

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The Short Strip ASIC (SSA) is one of the four front-end chips designed for the upgrade of the CMS Outer Tracker for the High Luminosity LHC. Together with the Macro-Pixel ASIC (MPA) it will instrument modules containing a strip and a macro-pixel sensor stacked on top of each other. The SSA provides both full readout of the strip hit information when triggered, and, together with the MPA, correlated clusters called stubs from the two sensors for use by the CMS Level-1 (L1) trigger system. Results from the first prototype module consisting of a sensor and two SSA chips are presented. The prototype module has been characterized at the Fermilab Test Beam Facility using a 120 GeV proton beam.

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First results from the CIC data aggregation ASIC for the Phase 2 CMS Outer Tracker

Cited by 3 publications

References 4 publications

CIC2: a radiation tolerant 65 nm data aggregation ASIC for the future CMS tracker

CIC2: a radiation tolerant 65 nm data aggregation ASIC for the future CMS tracker

CIC: a radiation tolerant 65 nm data aggregation ASIC for the future CMS tracking detector at LHC

Beam test performance of a prototype module with Short Strip ASICs for the CMS HL-LHC tracker upgrade

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