Fixed-point trigonometric functions on FPGAs

Dinechin, Florent de; Istoan, Matei; Sergent, Guillaume

doi:10.1145/2641361.2641375

Cited by 23 publications

(34 citation statements)

References 9 publications

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“…Various approaches for sin and cos were presented [33]. Moreover, FPGA vendors already offer Lookup tables for easier implementation [32]. Thus, it is possible to achieve desired hardware resources implementation of registers, LUT and, DSP units.…”

Section: Fig 8 Position and Velocity Estimation Of The Pll αβ-Trackermentioning

confidence: 99%

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Enhanced Pseudo-sensorless Bilateral Teleoperation by PLL αβ-tracker and FPGA

Hace

Franc

2014

Automatika

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Original scientific paperIn this paper, the problem of external sensors within bilateral teleoperation is addressed. We propose a Phase Locked Loop (PLL) αβ-tracker that presents an enhanced approach for position and velocity estimation. The proposed approach offers some advantages over the method presented in our previous research that was introduced to enable pseudo-sensorless teleoperation. Such approach applies PMLSM actuators with analog Hall sensors built in a motor housing. They allow obtaining sufficient position, velocity, and force information for teleoperation by a haptic interface. Furthermore, FPGA has been utilized for the implementation in order to achieve high control rate that was already introduced as a necessity in cutting edge performance systems. However, main advantages of the method presented in this paper is attributed to improved system performance due to the better signal-noise ratio and to enhanced flexibility of hardware resources consumption. Thus, high-performance bilateral control can be achieved. Such bilateral teleoperation with a dedicated haptic interface can significantly improve surgical robotics. The proposed approach was experimentally validated by the simple 1-DoF laboratory bilateral teleoperation system. Key words: Velocity Estimation, Phase Locked Loop, Bilateral Teleoperation, Haptics, FPGA Poboljšana pseudo-bezsenzorna bilateralna teleoperacija korištenjem PLL αβ estimatora i FPGA. Glavni predmet ovog rada je problematika korištenja eksternih senzora u procesu bilateralne teleoperacije. U radu je predložen αβ estimator temeljen na principu fazno zatvorene petlje (eng. Phase Locked Loop, PLL) koji se učinkovito koristi za problem istovremene estimacije pozicije i brzine. Predloženi pristup pruža odreîene prednosti u odnosu na metode koje smo prethodno razvili za ostvarenje pseudo-bezsenzorne teleoperacije. Pristup primjenjuje PMLSM aktuatore s analognim Hallovim sondama ugraîenih u metalno kućište. Oni se koriste za dobivanje dovoljno informacija o poziciji, brzini i sili, za teleoperaciju s haptičkim sučeljem. Nadalje, za omogućavanje izvoîenja upravljačkog algoritma s vrlo visokom frekvencijom u svrhu implementacije korišten je FPGA sklop, koji se već pokazao kao nužnost u primjeni na sustavima s visokom razinom performansi. Unatoč tome, glavna prednost metode koja je predložena u ovom radu odnosi se na poboljšanje performansi sustava zbog boljeg omjera signala i šuma te povećanu fleksibilnost potrošnje sklopovskih resursa. Prema tome, moguće je ostvariti bilateralno upravljanje s visokim performansama. Takva bilateralna teleoperacija s prilagoîenim haptičnim sučeljem može utjecati na značajna poboljšanja u kirurškoj robotici. Predloženi pristup je eksperimentalno validiran na jednostavnom bilateralnom teleoperacijskom sustavu s jednim stupnjem slobode.Ključne riječi: estimacija brzine, fazno zatvorena petlja, bilateralna teleoperacija, haptično sučelje, FPGA

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Section: Fig 8 Position and Velocity Estimation Of The Pll αβ-Trackermentioning

confidence: 99%

“…On the other hand, atan2 implementation also provides a little flexibility [34]. This is compared to sin and cos, presented in [32], not so effective. The hardware resources consumption may present an important factor within extensive mechatronic control systems.…”

Section: Fig 8 Position and Velocity Estimation Of The Pll αβ-Trackermentioning

confidence: 99%

Enhanced Pseudo-sensorless Bilateral Teleoperation by PLL αβ-tracker and FPGA

Hace

Franc

2014

Automatika

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“…An enlightening example (to our knowledge unpublished) is a third-order Taylor formula for the sine: sin(X) ≈ X − X 3 /6, which we use in [9]. This formula can be evaluated using two standard multiplications (to compute X 3 ), a multiplication by the constant 1/6, and a subtraction.…”

Section: Bit Heaps Enable Bit-level Algebraic Optimizationsmentioning

confidence: 99%

“…We use another option, with a variation of the divider by 3 from [10] that adds 3p bits to the bit heap, albeit after a delay. Table I shows properly truncated bit heaps in the context of a sine/cosine implementation [9], and gives the corresponding synthesis results (for smaller input sizes, the whole of X 3 /6 is simply tabulated).…”

Section: Bit Heaps Enable Bit-level Algebraic Optimizationsmentioning

confidence: 99%

“…A solution to the above issue is therefore to express as much as possible of the operators as bit heaps. We may then delegate their implementation (the actual code generation) to a [9] single, centralized, versatile bit heap framework. When a new FPGA appears, all we need is to update this one piece of code.…”

Section: A Versatile Bit Heap Implementation Simplifies Core Generationmentioning

confidence: 99%

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Arithmetic core generation using bit heaps

Brunie¹,

Dinechin

Istoan

et al. 2013

2013 23rd International Conference on Field Programmable Logic and Applications

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Abstract-A bit heap is a data structure that holds the unevaluated sum of an arbitrary number of bits, each weighted by some power of two. Most advanced arithmetic cores can be viewed as involving one or several bit heaps. We claim here that this point of view leads to better global optimization at the algebraic level, at the circuit level, and in terms of software engineering.To demonstrate it, a generic software framework is introduced for the definition and optimization of bit heaps. This framework, targeting DSP-enabled FPGAs, is developed within the opensource FloPoCo arithmetic core generator. Its versatility is demonstrated on several examples: multipliers, complex multipliers, polynomials, and discrete cosine transform.

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Fixed-Point Sine and Cosine

de Dinechin,

Kumm

2023

Application-Specific Arithmetic

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Fixed-point trigonometric functions on FPGAs

Cited by 23 publications

References 9 publications

Enhanced Pseudo-sensorless Bilateral Teleoperation by PLL αβ-tracker and FPGA

Enhanced Pseudo-sensorless Bilateral Teleoperation by PLL αβ-tracker and FPGA

Arithmetic core generation using bit heaps

Fixed-Point Sine and Cosine

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