Fixed-Width Multiplier with Simple Compensation Bias

Bhusare, Saroja S.; Bhaaskaran, V. S. Kanchana

doi:10.1016/j.mspro.2015.06.071

Cited by 4 publications

(2 citation statements)

References 7 publications

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“…Figure 3 demonstrates the area comparison of proposed RLNS multiplier with various FWM. The area of the proposed FW RLNS multiplier 16,668 µm 2 was comparably lesser than the existing multiplier such as standard, Direct Truncated Method (DTM), 29 Probability Estimation Bias (PEB), 30 standard and Truncated Multiplier (TM), 31 and Song's Fixed-width Multiplier (SFM), 32 respectively. The circuit layout area and power utilization in the proposed design are slightly lower than that of the existing FWM.…”

Section: Resultsmentioning

confidence: 93%

A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm

Rubia¹,

Sathishkumar²

2018

International Journal of Electrical Engineering & Education

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The Residue Logarithmic Number System (RLNS) in digital mathematics allows multiplication and division to be performed considerably quickly and more precisely than the extensively used Floating-Point number setups. RLNS in the pitch of large scale integrated circuits, digital signal processing, multimedia, scientific computing and artificial neural network applications have Fixed Width property which has equal number of in and out bit width; hence, these applications need a Fixed Width multiplier. In this paper, a Fixed Width-Floating-Point multiplier based on RLNS was proposed to increase the processing speed. The truncation errors were reduced by using Taylor series. RLNS is the combination of both the residue number system and the logarithmic number system, and uses a table lookup including all bits for expansion. The proposed scheme is effective with regard to speed, area and power utilization in contrast to the design of conservative Floating-Point mathematics designs. Synthesis results were obtained using a Xilinx 14.7 ISE simulator. The area is 16,668 µm2, power is 37 mW, delay is 6.160 ns and truncation error can be lessened by 89% as compared with the direct-truncated multiplier. The proposed Fixed Width RLNS multiplier performs with lesser compensation error and with minimal hardware complexity, particularly as multiplier input bits increment.

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Section: Resultsmentioning

confidence: 93%

A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm

Rubia¹,

Sathishkumar²

2018

International Journal of Electrical Engineering & Education

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“…The lookup table-based approximate multiplier produces approximate output based on the values in the memory block, [1,2] so that there are large memory requirements. In n-bit integer multiplication, the approximate multiplier with n-bit fixed-width output discards n low-order output bits [3][4][5][6][7]. The arithmetic-based multiplier adopts low-cost arithmetic operations to approximate exact multiplication with affordable accuracy degradation [1,2,[8][9][10][11][12][13][14][15][16][17][18][19][20][21][22].The logarithmic multiplier can suppress the worst-case relative error (rerr worst ) under its designed limitation.…”

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confidence: 99%

A low‐cost compensated approximate multiplier for Bfloat16 data processing on convolutional neural network inference

Kim¹

2021

ETRI Journal

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This paper presents a low‐cost two‐stage approximate multiplier for bfloat16 (brain floating‐point) data processing. For cost‐efficient approximate multiplication, the first stage implements Mitchell's algorithm that performs the approximate multiplication using only two adders. The second stage adopts the exact multiplication to compensate for the error from the first stage by multiplying error terms and adding its truncated result to the final output. In our design, the low‐cost multiplications in both stages can reduce hardware costs significantly and provide low relative errors by compensating for the error from the first stage. We apply our approximate multiplier to the convolutional neural network (CNN) inferences, which shows small accuracy drops with well‐known pre‐trained models for the ImageNet database. Therefore, our design allows low‐cost CNN inference systems with high test accuracy.

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Low-biased probabilistic multipliers using complementary inaccurate compressors

Kim,

Del Barrio

2024

Digital Signal Processing

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Fixed-Width Multiplier with Simple Compensation Bias

Cited by 4 publications

References 7 publications

A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm

A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm

A low‐cost compensated approximate multiplier for Bfloat16 data processing on convolutional neural network inference

Low-biased probabilistic multipliers using complementary inaccurate compressors

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