Flash ADC Utilizing Offset Voltage Variation With Order Statistics Based Comparator Selection

Kitamura, Takehiro; Islam, Mahfuzul; Hisakado, Takashi; Wada, Osami

doi:10.1109/isqed51717.2021.9424288

Cited by 3 publications

(5 citation statements)

References 5 publications

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“…To optimize the distribution, we define an objective function to evaluate linearity. INLs of order statistic-based flash ADC can be represented as follows [9].…”

Section: Objective Functionmentioning

confidence: 99%

“…To validate the above optimization, we evaluate DNL and INL theoretically using the method in Ref. [9]. Figure 8 illustrates the relationship between INL and the number of comparators.…”

Section: Validationmentioning

confidence: 99%

“…Adding analog circuitry, such as the DACs, will increase the design cost. This motivates us to investigate a time-domain digital calibration technique to eliminate the need for offset voltage measurement [9], [10].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design of Reference-free Flash ADC With On-chip Rank-based Comparator Selection Using Multiple Comparator Groups

Kitamura,

Hisakado,

Wada

et al. 2024

IPSJ Transactions on System LSI Design Methodology

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Statistical element selection has been proposed to solve the offset voltage variation problem for a flash ADC. A calibration method based on order statistics has been proposed for statistical selection that does not require offset voltage measurement. This paper presents a design methodology of flash ADC with such calibration using multiple comparator groups. We validate our proposal with measurement results from test chips fabricated in a commercial 65 nm general-purpose process. Measurement results confirm that rank-based comparator selection achieves a reference-free ADC. Compared to the baseline ADC, where only one group of comparators is used, the ADC with three groups significantly increases the linearity and input range under the same power consumption. As no reference voltage and DACs are required, the proposed ADC design will help realize ADCs in advanced process nodes with lower power consumption.

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“…To optimize the distribution, we define an objective function to evaluate linearity. INLs of order statistic-based flash ADC can be represented as follows [9].…”

Section: Objective Functionmentioning

confidence: 99%

“…To validate the above optimization, we evaluate DNL and INL theoretically using the method in Ref. [9]. Figure 8 illustrates the relationship between INL and the number of comparators.…”

Section: Validationmentioning

confidence: 99%

See 1 more Smart Citation

Design of Reference-free Flash ADC With On-chip Rank-based Comparator Selection Using Multiple Comparator Groups

Kitamura,

Hisakado,

Wada

et al. 2024

IPSJ Transactions on System LSI Design Methodology

Self Cite

View full text Add to dashboard Cite

show abstract

“…As a calibration method to eliminate the need for DACs, we previously proposed a flash ADC architecture that selects comparators based on the rankings of the offset voltages [15]. By calculating the rankings from the distribution of offset voltages based on order statistics, equally spaced offset voltages can be obtained.…”

Section: Introductionmentioning

confidence: 99%

“…Thus, the ranking estimation can be achieved by time-domain measurements, which can easily be implemented on-chip. This paper is an extension of our prior work [15] with the following additional contents. In Sect.…”

Section: Introductionmentioning

confidence: 99%

Order Statistics Based Low-Power Flash ADC with On-Chip Comparator Selection

Kitamura

Islam

Hisakado

et al. 2022

IEICE Trans. Fundamentals

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High-speed flash ADCs are useful in high-speed applications such as communication receivers. Due to offset voltage variation in the sub-micron processes, the power consumption and the area increase significantly to suppress variation. As an alternative to suppressing the variation, we have developed a flash ADC architecture that selects the comparators based on offset voltage ranking for reference generation. Specifically, with the order statistics as a basis, our method selects the minimum number of comparators to obtain equally spaced reference values. Because the proposed ADC utilizes offset voltages as references, no resistor ladder is required. We also developed a time-domain sorting mechanism for the offset voltages to achieve on-chip comparator selection. We first perform a detailed analysis of the order statistics based selection method and then design a 4-bit ADC in a commercial 65-nm process and perform transistor-level simulation. When using 127 comparators, INLs of 20 virtual chips are in the range of −0.34 LSB/+0.29 LSB to −0.83 LSB/+0.74 LSB, and DNLs are in the range of −0.33 LSB/+0.24 LSB to −0.77 LSB/+1.18 LSB at 1-GS/s operation. Our ADC achieves the SNDR of 20.9 dB at Nyquist-frequency input and the power consumption of 0.84 mW.

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Performance Improvement of Order Statistics Based Flash ADC Using Multiple Comparator Groups

Kitamura

Islam

Hisakado

et al. 2022

2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)

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Flash ADC Utilizing Offset Voltage Variation With Order Statistics Based Comparator Selection

Cited by 3 publications

References 5 publications

Design of Reference-free Flash ADC With On-chip Rank-based Comparator Selection Using Multiple Comparator Groups

Design of Reference-free Flash ADC With On-chip Rank-based Comparator Selection Using Multiple Comparator Groups

Order Statistics Based Low-Power Flash ADC with On-Chip Comparator Selection

Performance Improvement of Order Statistics Based Flash ADC Using Multiple Comparator Groups

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