Flat-High-Gain Design and Noise Optimization in SiGe Low-Noise Amplifier for S–K Band Applications

Li, Zhenrong; Liu, Boyu; Duan, Yupeng; Wang, Zeyuan; Zhang, Yiqi

doi:10.1007/s00034-020-01616-2

Cited by 7 publications

(5 citation statements)

References 27 publications

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“…However, for efficient utilization of the silicon chip area, the maximum capacitance value is set to 50 pF. Thus, we need to design an OTA with reduced Gm which makes it necessary to incorporate a transconductance reduction technique [19]- [22]. The literature review done for this work focusing on OTAbased LPF in biomedical application substantiate different design techniques used for Gm reduction, moreover, each technique is trading-off with at least one key performance parameter.…”

Section: Figure 1 Block Diagram Of Analog Front End Processing Circuitmentioning

confidence: 99%

Low power CMOS Gm-C based low pass filter for front end neural signal processing

Dixit,

Srivastava,

Kumar

et al. 2024

IJPEDS

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The sub 100 µV voltage levels and sub 100 Hz frequency range makes the processing of most popular signal electroencephalograph (EEG) for brain functionality analysis, a complex task. The low frequency content of EEG (useful signals below 70 Hz) is commonly used for diagnosis of various brain related disorders making low-pass filter (LPF) a key block in front-end processing as noise reduction and resolution enhancement is crucial for precise recovery of these information. This paper is aimed to design reduced transconductance (Gm) based low power and small area CMOS LPF with cutoff frequency (fc) around 70 Hz. The proposed design is simulated using Cadence virtuoso tool and gives cut-off frequency of 72.958 Hz with low output noise of 3.0609 µV/√Hz and power consumption of 264.060 nW at operating voltage of 0.4 V. The simulation results show linearity of performance over -40 to 100 °C. Layout of circuit takes up area of 86.74×81.21 µm and post layout simulation shows 5% variation in power consumption as compared to pre layout simulations.

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Section: Figure 1 Block Diagram Of Analog Front End Processing Circuitmentioning

confidence: 99%

Low power CMOS Gm-C based low pass filter for front end neural signal processing

Dixit,

Srivastava,

Kumar

et al. 2024

IJPEDS

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“…Circuit-1 represents the proposed CC amplifier with user defined PSpice model of opposite polarity matched BJTs under Sziklai pair topology. Circuit-2 is the small-signal CC amplifier user defined PSpice model of matched PNP transistors under Darlington pair topology whereas Circuit-3 is small-signal CC amplifier with user defined PSpice model of PNP transistor (18) .…”

Section: Qualitative Comparison With Other Configurationsmentioning

confidence: 99%

“…If R P is removed from this design, current gain almost remains constant however voltage shift down from 111.37 to 67.04 with narrow band signal. However, in present investigation, biasing resistance R P of 1Ω is used to preserve its voltage amplification property and to enhance the frequency band (18)(19)(20) . Figure 9 represents the voltage gain and current gain of the proposed amplifier with respect to frequency at 180nm technology under Cadence Virtuoso and Spectre Simulation Software.…”

mentioning

confidence: 99%

Design and Analysis of Wideband PNP Sziklai Common Collector Amplifier with High Current Gain

Shukla,

Arshad,

Soni

et al. 2023

IJST

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Objective: Objective of the manuscript is to introduce a novel idea of designing a small-signal common collector (emitter follower) amplifier with user-defined PSpice model of PNP Sziklai pair. Method: A circuit simulation program is developed on the PSpice simulation platform to design and study the proposed amplifier circuit. Small-signal AC equivalent circuit analysis authenticates the proposed amplifier design and selection of biasing components. The proposed amplifier is also implemented on Cadence Virtuoso Simulation software at 180nm technology to validate the design by performing its layout and postlayout simulation. Findings: The proposed circuit gives high current gain and smaller gain fluctuations (β ) due to environmental parameter variations. The effect of variation in stage current gain of Sziklai pair components is observed under different operating conditions. Equivalent circuit analysis, noise performance, and the effect of temperature on the performance of the proposed circuit are widely discussed. Other possible circuit structures with a similar concept of design are also discussed as special cases. Highly stable amplifier current gain as well as device current gain, high amplifier voltage gain, device voltage gains below unity, and low harmonic distortion are prime features of proposed circuit. The problem of finding a matched pair of BJTs for the Sziklai pair is also addressed in the proposed design. The linear distortion-less operation of this circuit, combined with its very high current gain, makes it a suitable candidate for instrumentation amplifiers with wide operating frequency range. The proposed amplifier takes up (10.105 x 10.055) µm 2 of area at 180nm technology. The results of pre-layout and post-layout AC responses show that there is a close resemblance between the parameters before and after the layout, which promotes the usability and design of the proposed amplifier. Novelty: The idea explored in the manuscript is entirely new and first time announced by authors.

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“…Apart from this, proposed pair with CE and CC amplifier also consumes very low amount of power in mW range. In addition, total power consumption can be further reduced to μW range by reducing supply voltage, at the cost of decreased voltage gain, current gain and bandwidth [18]. It is also found that total harmonic distortion (THD) of CE amplifier is lower than CC amplifier, however range of operation of CC amplifier (1 μV-30 mV) is higher than CE amplifier (10 μV-1 mV).…”

Section: Performancementioning

confidence: 99%

Novel complementary Sziklai pair based high gain low noise small-signal amplifiers

Shukla,

Arshad,

Srivastava

2023

IJPEDS

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A new paired configuration of opposite polarity BJTs, the “complementary Sziklai pair” is introduced in the series of multi-BJT-based devices like Darlington and Sziklai pair, and its viability is tested in small-signal common emitter (CE) and common collector (CC) amplifier configurations. The Darlington and Sziklai both face the problem of poor frequency response at a higher frequency which is addressed by the proposed configuration. The proposed pair with CE amplifier holds class-A amplification property with a high voltage gain of 200.05, a high current gain of 11.62, wider bandwidth of 1.64 MHz, and a low THD of 1.29E-6%, hence supports the potential of wide applicability in analog communication. Similarly, the proposed pair with CC configuration produces approximately a unit current gain of 0.99 with wider bandwidth of 1.90 MHz and low THD of 1.76E-6%, therefore it can be used as a current buffer in a generalized current follower circuit. Conclusively, the device structure of this new BJT pair may be considered the third consecutive member of the series of Darlington pair and Sziklai pair. The layout of the proposed CE and CC amplifier occupy small areas of 158.30 μm2 (10.23×15.47 μm) and 141.16 μm2 (10.20×13.84 μm) respectively in 180 nm process technology.

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Flat-High-Gain Design and Noise Optimization in SiGe Low-Noise Amplifier for S–K Band Applications

Cited by 7 publications

References 27 publications

Low power CMOS Gm-C based low pass filter for front end neural signal processing

Low power CMOS Gm-C based low pass filter for front end neural signal processing

Design and Analysis of Wideband PNP Sziklai Common Collector Amplifier with High Current Gain

Novel complementary Sziklai pair based high gain low noise small-signal amplifiers

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