Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping

Li, Xingchen; Yuan, Zhihang; Guan, Yijin; Sun, Guangyu; Zhang, Tao; Wei, Rongshan; Niu, Dimin

doi:10.1109/tcad.2022.3146204

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A Ddr Access Latency and Row Conflicts2

×P Rob+ T G+t G+t G+t G+t G+t G T Gn1

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2023

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(3 citation statements)

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“…When accessing DDR4, the Burst Length 8 (BL8) mode is commonly used, which means that each memory access command can read or write a sequence of 8 bytes as a group [15]. For a fixed set of data, there are two DDR4 characters [16] that result in different access latency values depending on the memory access sequence:…”

Section: A Ddr Access Latency and Row Conflictsmentioning

confidence: 99%

“…Summarizing these characters, it is recommended to avoid making consecutive accesses to different rows within a single bank as far as possible. It helps minimize the occurrence of row conflicts within the same bank [16]. The address of a data group can be represented as (row, bank, bank group, first column: last column).…”

Section: A Ddr Access Latency and Row Conflictsmentioning

confidence: 99%

“…The probability that two adjacent rows locate in the same bank, i.e. P rob, is P rob = [1 − (pb) 16 ] × (pb) 3 ≈ 0.125.…”

Section: ×P Rob+ T G+t G+t G+t G+t G+t G T Gnmentioning

confidence: 99%

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