FlexAmata: A Universal and Efficient Adaption of Applications to Spatial Automata Processing Accelerators

Sadredini, Elaheh; Rahimi, Reza; Lenjani, Marzieh; Stan, Mircea R.; Skadron, Kevin

doi:10.1145/3373376.3378459

Cited by 18 publications

(9 citation statements)

References 51 publications

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“…While a more recent benchmark suite AutomataZoo [33] extends ANMLZoo with larger benchmarks. ANMLZoo is selected in our evaluation because (1) the AP chip with up to 48k states only supports ANMLZoo, (2) evaluating an automata accelerator on large benchmarks in AutomataZoo is excessively time consuming, and (3) prior studies on automata acceleration, including CA [29], Impala [24], AP [10], FlexAmata [26], and Grapefruit [22], all adopt ANMLZoo for evaluation. 10MB inputs are used for all evaluations.…”

Section: Evaluation Methodologymentioning

confidence: 99%

CAMA: Energy and Memory Efficient Automata Processing in Content-Addressable Memories

Huang¹,

Chen²,

Li³

et al. 2021

Preprint

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Accelerating finite automata processing is critical for advancing real-time analytic in pattern matching, data mining, bioinformatics, intrusion detection, and machine learning. Recent in-memory automata accelerators leveraging SRAMs and DRAMs have shown exciting improvements over conventional digital designs. However, the bit-vector representation of state transitions used by all state-of-the-art (SOTA) designs is only optimal in processing worst-case completely random patterns, while a significant amount of memory and energy is wasted in running most real-world benchmarks.We present CAMA, a Content-Addressable Memory (CAM) enabled Automata accelerator for processing homogeneous nondeterministic finite automata (NFA). A radically different state representation scheme, along with co-designed novel circuits and data encoding schemes, greatly reduces energy, memory, and chip area for most realistic NFAs. CAMA is holistically optimized with the following major contributions: (1) a 16×256 8-transistor (8T) CAM array for state matching, replacing the 256×256 6T SRAM array or two 16×256 6T SRAM banks in state-of-theart (SOTA) designs; (2) a novel encoding scheme that enables content searching within 8T SRAMs and adapts to different applications; (3) a reconfigurable and scalable architecture that improves efficiency on all tested benchmarks, without losing support for any NFA that's compatible with SOTA designs; (4) an optimization framework that automates the choice of encoding schemes and maps a given NFA to the proposed hardware.Two versions of CAMA, one optimized for energy (CAMA-E) and the other for throughput (CAMA-T), are comprehensively evaluated in a 28nm CMOS process, and across 21 real-world and synthetic benchmarks. CAMA-E achieves 2.1×, 2.8×, and 2.04× lower energy than CA, 2-stride Impala, and eAP. CAMA-T shows 2.68×, 3.87× and 2.62× higher average compute density than 2-stride Impala, CA, and eAP. Both versions reduce the chip area required for the largest tested benchmark by 2.48× over CA, 1.91× over 2-stride Impala, and 1.78× over eAP.

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Section: Evaluation Methodologymentioning

confidence: 99%

CAMA: Energy and Memory Efficient Automata Processing in Content-Addressable Memories

Huang¹,

Chen²,

Li³

et al. 2021

Preprint

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“…SIMD and row-wide bitwise approaches: Bank-level SIMD approaches [24,30] or subarray-level bit-parallel and bit-serial approaches [21,35,[43][44][45][46][47][48]51] perform the same operation on multiple aligned words. These approaches cannot efficiently support SpMV and SpMSpV.…”

Section: Related Workmentioning

confidence: 99%

Gearbox

Lenjani

Ahmed

Stan

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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Processing-in-memory (PIM) minimizes data movement overheads by placing processing units near each memory segment. Recent PIMs employ processing units with a SIMD architecture. However, kernels with random accesses, such as sparse-matrix-dense-vector (SpMV) and sparse-matrix-sparse-vector (SpMSpV), cannot effectively exploit the parallelism of SIMD units because SIMD's ALUs remain idle until all the operands are collected from local memory segments (memory segment attached to the processing unit) or remote memory segments (other segments of the memory).For SpMV and SpMSpV, properly partitioning the matrix and the vector among the memory segments is also very important. Partitioning determines (i) how much processing load will be assigned to each processing unit and (ii) how much communication is required among the processing units.In this paper, first, we propose a highly parallel architecture that can exploit the available parallelism even in the presence of random accesses. Second, we observed that, in SpMV and SpMSpV, most of the remote accesses become remote accumulations with the right choice of algorithm and partitioning. The remote accumulations could be offloaded to be performed by processing units next to the destination memory segments, eliminating idle time due to remote accesses. Accordingly, we introduce a dispatching mechanism for remote accumulation offloading. Third, we propose Hybrid partitioning and associated hardware support. Our partitioning technique enables (i) replacing remote read accesses with broadcasting (for only a small portion of data that will be read by all processing units), (ii) reducing the number of remote accumulations, and (iii) balancing the load.Our proposed method, Gearbox, with just one memory stack, delivers on average (up to) 15.73× (52×) speedup over a server-class GPU, NVIDIA P100, with three stacks of HBM2 memory.

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“…The authors expand their work to support AWS F1 instances [25] and to allow a fast reconfiguration of different REs that exploit the same NFA structure [6]. On top of these approaches, other authors propose a compiler framework called FlexAmata that aims at optimizing the automata representation also considering different alphabet symbols bitwidth [29], further extended to exploit either LUT-or BRAM-based designs [26]. CICERO is, instead, a specialized but flexible architecture that can support several different REs thanks to the custom ISA and the compiler-based framework.…”

Section: Related Workmentioning

confidence: 99%

“…The Automata Processor (AP) was an outstanding spatial reconfigurable architecture that embedded a target automaton into the reconfigurable fabric [13,37]. While it was a promising solution with high performance [29,42] and no FPGA bitstream overhead [24,38], only simulation results of the AP were reported while we show a prototype executed on FPGA [6] 4 .…”

Section: Related Workmentioning

confidence: 99%

“…Despite significant algorithmic improvements, software solutions cannot keep pace with the increasing size of the processed data (either input strings or REs). For this reason, hardware acceleration is a valid alternative for computationally-intensive kernels such as those for RE matching [3,4,7,14,26,29,31,40]. In this scenario, reconfigurable FPGA devices represent a viable solution to boost the matching process while keeping a low energy profile.…”

Section: Introductionmentioning

confidence: 99%

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CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching

Parravicini

Conficconi

Sozzo

et al. 2021

ACM Trans. Embed. Comput. Syst.

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Regular Expression (RE) matching is a computational kernel used in several applications. Since RE complexity and data volumes are steadily increasing, hardware acceleration is gaining attention also for this problem. Existing approaches have limited flexibility as they require a different implementation for each RE. On the other hand, it is complex to map efficient RE representations like non-deterministic finite-state automata onto software-programmable engines or parallel architectures. In this work, we present CICERO , an end-to-end framework composed of a domain-specific architecture and a companion compilation framework for RE matching. Our solution is suitable for many applications, such as genomics/proteomics and natural language processing. CICERO aims at exploiting the intrinsic parallelism of non-deterministic representations of the REs. CICERO can trade-off accelerators’ efficiency and processors’ flexibility thanks to its programmable architecture and the compilation framework. We implemented CICERO prototypes on embedded FPGA achieving up to 28.6× and 20.8× more energy efficiency than embedded and mainstream processors, respectively. Since it is a programmable architecture, it can be implemented as a custom ASIC that is orders of magnitude more energy-efficient than mainstream processors.

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FlexAmata: A Universal and Efficient Adaption of Applications to Spatial Automata Processing Accelerators

Cited by 18 publications

References 51 publications

CAMA: Energy and Memory Efficient Automata Processing in Content-Addressable Memories

CAMA: Energy and Memory Efficient Automata Processing in Content-Addressable Memories

Gearbox

CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching

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