FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection Using Reconfigurable ASIP

Abstract

This paper describes the implementation of a multi-mode MIMO detector based on the concept of partially reconfigurable ASIP (rASIP). The multi-mode detector can support three different detection algorithms which are the Maximum Ratio Combining, the linear Minimum Mean Square Error (MMSE) detection, and the MMSE Successive Interference Cancellation. The detection algorithms also support different antenna configurations and modulation schemes. The rASIP is based on a Coarse-Grained Reconfigurable Architecture (CGRA), which is designed for efficient architectural support of matrix operations. A matrix inversion algorithm, which is used for the preprocessing of different detection algorithms, is mapped on the CGRA. By integrating a processor with the CGRA, the variations in the control path of different algorithm configurations can be handled efficiently. To the best of our knowledge, we show, for the first time that, a CGRAbased multi-mode MIMO detection is extremely efficient and matches the performance of dedicated ASIC implementation.

Ingredients of Adaptability: A Survey of Reconfigurable Processors

“…It shows that efficient design points can be obtained by exploring instruction decoding, computation, and communication patterns. This theoretical insight of DeHon [23] confirms the observations on prior experimental results and has since been empirically validated by many designs [30,31].…”

“…It is shown that the optimal runtime of ( 3 / ) is achieved only when a particular distribution of local tasks and communication bandwidth is maintained. This leads to direct practical implementation suggestions [31].…”

“…Reconfigurable processors are capable of supporting instruction-level and data-level parallelism with mixed granularity and therefore remain the ideal implementation option when all these features are present in a certain application. In absence of the right set of profiling tools to rate the processors for certain applications, the approach that has been taken by current designers is to perform a bottom-up kernel-specific design [79] and then apply that architecture to an application domain [31]. The structural and domain-wise classification of reconfigurable processors is presented in Figure 7.…”

“…For the W-CDMA protocol, a partially reconfigurable processor is designed in [74]. For the MIMO-OFDM multimode detector FLEXDET [31] is proposed. ADRES [66] is designed for Software Defined Radio applications.…”

“…A third implementation option, which allows picking up a customizable processor with a custom-designed reconfigurable fabric, is offered by few designs, for example, ADRES [66]. Here the goal is to completely tune the processing and reconfigurability to a specific target domain [31,80].…”