1) Introduction, the front end ideaCognitive multi-radio front-end design is a challenge in terms of efficiency and wide bandwidth capability because it should be able to adapt the characteristics of any mobile and WLAN (Wireless Local Area Network) standards in L, S and C band. To summarize the functionality of this part of the transmitter architecture, the front end should be able to transmit at high power level a set of different wide modulation schemes such as multi-carrier ones, for (worst) example OFDM (Orthogonal Frequency Division Multiplex) 20 MHz, from 1 GHz to almost 6 GHz of carrier frequency. This implies the designer to combine high efficiency architecture with linearity and possibility of low power control. For several years, transmitters architectures based on high efficiency switched power amplifiers (PA) have been focused on, especially the class E PA [1][2] [3] which have been demonstrated to be useful in OFDM polar architecture such as EER [4] where amplitude information (supply modulation or PWM/Sigma-Delta coding) and power control (supply modulation) can be introduced. The idea of this paper is based on the possibility of detuning the class E PA with parallel RF switched capacitors. This principle was presented briefly in [5] with a 50 Ohms load, but was not yet studied in the real case of the antenna load. That is to say, the originality of this paper is to develop a methodology for the co-design of the class E PA with wideband and multibands antennas. We will underline the importance of the wideband antenna characteristic on the PA performance. The antenna adapted to multi-radio can present some rejection at frequencies where no standard exists in WLAN and mobile networks, from 2.7 GHz to 3.4 GHz for example. Taking the realistic wideband load due to the antenna changes the performances of the class E PA, and so the front end characteristics. This will be discussed in the following part.
2) Considered Class E topology with a E_PHEMT modelR 0.732 L 1.365 P V R = = = = = = = Figure 1 : Parallel topology for the class E (parallel inductor)The topology used in this paper is the "parallel topology" presented in [3] and [5], and is reported in figure 1. Its design employs a parallel inductor and suppresses the biasing inductance, with dedicated optimum values for the load resistance R 2 , parallel capacitor C 2 and inductor L 2 reported in figure 1. Simulation reports that the tuning of the class E network is directly dependent of the shunt capacitor value and a modification of the parallel capacitance enable a frequency shift control of the class E PA. To simulate this accordability, we choose a high frequency transistor for designing the PA and the parallel switches (with series capacitor). The transistor used to conceive the front-end is a GaAs E-PHEMT, Avago ATF50189. It's a high linearity, medium power FET : 29dBm output power at 1dB gain 978-1-4244-2642-3/08/$25.00 ©2008 IEEE