Flexible and Dynamically Reconfigurable FPGA-Based FS-FBMC Baseband Modulator

Ferreira, Mário Lopes; Ferreira, João Canas

doi:10.1109/iscas.2018.8351060

Cited by 8 publications

(7 citation statements)

References 20 publications

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“…Zynq 7000 (ZC706) 36 36 37 The last aspect to consider is the comparison of the proposal with other previous works focused on mixed HW/SW implementations using a SoC. This requires to be dealt with carefully, as these previous implementations are only hardware architectures, not involving any software part, and the mathematical definition of the modulation is not exactly the same as the FBMC studied here.…”

Section: -Ascet 1-ascet 2-ascetmentioning

confidence: 99%

“…In [35] a Filter-Bank Multi-Carrier with Offset Quadrature Amplitude Modulation (FBMC/OQAM) hardware implementation is proposed, which provides a complexity reduction in terms of computational and memory resources in a SoC Xilinx Zynq® 7000 device. In [36] a reconfigurable FPGA-based Frequency Spreading FBMC (FS-FBMC) baseband modulator is proposed, whose design is resource-efficient, due to hardware virtualization. Finally, in [21] an architecture based on DCT4e is presented to implement a FBMC system, as well as a comparative analysis, in terms of resource consumption, performance, and precision.…”

Section: -Ascet 1-ascet 2-ascetmentioning

confidence: 99%

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Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core Solution

2020

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Power-Line Communication (PLC) employs multi-carrier modulations, such as Filter-Bank Multi-Carrier (FBMC), to improve communications through the PLC channel and provide an efficient use of the spectrum, thus allowing higher data rates. Since one of the main drawbacks is the noisy channel with multipath and frequency-selective fading, the receiver typically includes a channel estimator and equalizer, at the expense of increasing the computational load and complexity of that receiver and making it difficult to obtain realtime solutions. In this context, this work proposes a heterogeneous System-on-Chip (SoC) architecture for the real-time implementation of a FBMC transmultiplexer that involves the channel estimation and equalization at the reception stage. For that purpose, the performance of a multi-core approach is evaluated for both the Zynq® 7000 SoC and the Zynq® UltraScale+ (US+) devices, by using a single-, dual-and quad-core solution to perform the channel estimation and the calculation of the equalizer coefficients in the ARM processor available in the proposed architecture. Two approaches have been analysed for the necessary synchronization among cores; one based on atomic instructions and the other one on interrupts. The dualcore proposal in both Zynq® 7000 and Zynq® US+ provides a x2 acceleration compared to the single-core proposal, whereas the quad-core one in Zynq® US+ does not provide a x4 acceleration as expected, due to the timing overheads of the synchronization among cores imposed by the data dependencies existing in these tasks. Experimental results include the evaluation of the processing times for each task in the algorithm, as well as the acceleration obtained by each proposal. The proposed architecture can be easily applied to other processing algorithms that may take advantage of the parallelism provided by the multi-core approach in a more efficient way, depending on their data dependencies.

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Section: -Ascet 1-ascet 2-ascetmentioning

confidence: 99%

Section: -Ascet 1-ascet 2-ascetmentioning

confidence: 99%

Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core Solution

2020

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“…Nadal et al [24] and Berg et al [25] presented FPGA-based implementations for polyphase network FBMC modulators. Alternatively, we showed that, despite its higher computational complexity, the Frequency Spreading (FS) approach is a convenient scheme for FPGA-based FBMC designs and proposed a flexible and resource-efficient variant of an FS-FBMC baseband modulator [26].…”

Section: Background and Related Workmentioning

confidence: 99%

“…Regarding the hardware implementations for the baseband modulator datapaths, we will describe the UFMC modulator design in more detail, and for OFDM and FBMC, we refer to our previous works [22,26]. The implemented modulator datapaths have AXI4-Stream-compatible input/output data interfaces, and all arithmetic operations are done in fixed-point precision, considering real and imaginary parts represented in the Q5.11 format.…”

Section: Overlap Andaddmentioning

confidence: 99%

An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios

Ferreira

2018

Electronics

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The next evolution in cellular communications will not only improve upon the performance of previous generations, but also represent an unparalleled expansion in the number of services and use cases. One of the foundations for this evolution is the design of highly flexible, versatile, and resource-/power-efficient hardware components. This paper proposes and evaluates an FPGA-oriented baseband processing architecture suitable for communication scenarios such as non-contiguous carrier aggregation, centralized Cloud Radio Access Network (C-RAN) processing, and 4G/5G waveform coexistence. Our system is upgradeable, resource-efficient, cost-effective, and provides support for three 5G waveform candidates. Exploring Dynamic Partial Reconfiguration (DPR), the proposed architecture expands the design space exploration beyond the available hardware resources on the Zynq xc7z020 through hardware virtualization. Additionally, Dynamic Frequency Scaling (DFS) allows for run-time adjustment of processing throughput and reduces power consumption up to 88%. The resource overhead for DPR and DFS is residual, and the reconfiguration latency is two orders of magnitude below the control plane latency requirements proposed for 5G communications.waveforms (FBMC, UFMC, GFDM) intermingled with a variety of 3G and 4G waveforms" [3]. In heavily used portions of the spectrum, such as the sub-6 GHz band, multi-waveform coexistence requires Dynamic Spectrum Access (DSA) and Carrier Aggregation (CA) techniques to achieve a more efficient spectrum utilization [1].Other important factors in 5G NR are cost minimization and energy efficiency. Cloud Radio Access Networks (C-RANs) attempt to achieve a more efficient energy consumption and resource allocation by deploying a central Baseband processing Unit (BBU) that serves multiple Remote Radio Heads (RRHs) [4]. This network architecture relies on reconfigurable hardware modules to implement BBUs supporting the different access technologies and modes of operation used by RRHs.The realization of the 5G vision will strongly rely on the design of hardware infrastructure adjusted to the challenges imposed by future wireless communications. Regarding digital baseband processing, hardware designs should be: (1)flexible to support multiple services requirements, waveforms, and numerologies; (2) evolvable/forward-compatible to be easily upgradeable with new functionalities and future modes of operation, thus extending the system's duty lifetime; (3) energy-efficient and (4) cost-effective. FPGAs are convenient platforms to design systems with these characteristics. Apart from their capacity for parallel intensive computation, FPGAs feature a high degree of flexibility not only at design time, but also at runtime, through Dynamic Partial Reconfiguration (DPR) [5]: the ability to reconfigure portions of FPGA logic fabric (reconfigurable regions) while the other portions remain unchanged and running. This increases the FPGA functional density, as mutually-exclusive circuits/functionalities are implemented o...

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“…Não foi encontrada diferença estatisticamente significativa na comparação entre QV com a presença de HA e DM. LUCCHETTI et al, 2012;FERREIRA;YOSHITOME, 2010;ALENCAR et al, 2012;DEL-DUCA et al, 2012; FREIRE; MENDONÇA; COSTA, 2012).…”

Section: Qualidade De Vida E Doenças Crônicas Não Transmissíveisunclassified

Perfil da saúde geral e qualidade de vida de idosos de uma instituição de longa permanência do município de Bauru

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Lauris, pelas importantes contribuições no meu Exame Geral de Qualificação. À Aline, Angela, Elen, Patrícia e Rafa, pelas revisões, sugestões e auxílios prestados durante o desenvolvimento deste trabalho. Aos Professores do Departamento de Saúde Coletiva, pelos valiosos conhecimentos transmitidos ao longo deste curso e pelo auxílio em todos os momentos. À Faculdade São Lucas e todos os Professores da graduação, em especial às Professoras Viviane, Karol e Lidiane, pela confiança e ensinamentos. Vocês também são responsáveis por esta conquista. Às funcionárias do Departamento, Rosa, Sílvia e Marta, pelo respeito, compromisso e cordialidade que sempre dispensaram a mim. As amigas, Aline, Angela, Adriana e Érica, por terem me acolhido tão bem quando cheguei a Bauru. Vocês se tornaram minha família Bauruense. Obrigada pela atenção e carinho. As minhas amigas, Nara, Luana, Lenise e Irla, sou grata pela amizade, torcida, companheirismo e os bons momentos vividos em cada visita a Porto Velho. À Capes pelo auxílio financeiro ao longo do desenvolvimento deste estudo. Por fim, agradeço a todos que não foram citados aqui, mas que de alguma forma colaboraram e torceram para o desenvolvimento deste trabalho. Meu muito obrigada a todos vocês.

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Flexible and Dynamically Reconfigurable FPGA-Based FS-FBMC Baseband Modulator

Cited by 8 publications

References 20 publications

Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core Solution

Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core Solution

An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios

Perfil da saúde geral e qualidade de vida de idosos de uma instituição de longa permanência do município de Bauru

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