Flexible cache error protection using an ECC FIFO

Yoon, Doe Hyun; Erez, Mattan

doi:10.1145/1654059.1654109

Cited by 25 publications

(8 citation statements)

References 30 publications

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“…Multibit memory errors have been observed in SRAM soft error evaluation experiments [22,29]. Yoon et al [42,43] designed approaches to virtualize ECC for main memory so as to increase its flexibility and offload expensive ECC error correction for last-level caches to DRAM. Gold et al [12] observed that multi-bit error detection and correction in L1 caches are more expensive in terms of performance, power, and area even for reasonable sizes.…”

Section: Related Workmentioning

confidence: 99%

Compiler-assisted detection of transient memory errors

2014

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The probability of bit flips in hardware memory systems is projected to increase significantly as memory systems continue to scale in size and complexity. Effective hardware-based error detection and correction require that the complete data path, involving all parts of the memory system, be protected with sufficient redundancy. First, this may be costly to employ on commodity computing platforms, and second, even on high-end systems, protection against multi-bit errors may be lacking. Therefore, augmenting hardware error detection schemes with software techniques is of considerable interest.In this paper, we consider software-level mechanisms to comprehensively detect transient memory faults. We develop novel compile-time algorithms to instrument application programs with checksum computation codes to detect memory errors. Unlike prior approaches that employ checksums on computational and architectural states, our scheme verifies every data access and works by tracking variables as they are produced and consumed. Experimental evaluation demonstrates that the proposed comprehensive error detection solution is viable as a completely software-only scheme. We also demonstrate that with limited hardware support, overheads of error detection can be further reduced.

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Section: Related Workmentioning

confidence: 99%

Compiler-assisted detection of transient memory errors

2014

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“…There are two basic mechanisms underlying Virtualized ECC: an augmented virtual memory (VM) interface that allows a separate virtual-to-physical mapping for data and for its associated redundant ECC information; and a generalization of DRAM ECC into a two-tiered protection mechanism, where a tier-one error code (T1EC) is used to detect errors on every access and a tiertwo error code (T2EC) is only needed when an error is actually detected [33,48,49]. Figure 2 compares traditional VM, with its fixed relation between data and ECC, and the decoupled two-tier approach of Virtualized ECC.…”

Section: Virtualized Ecc Architecturementioning

confidence: 99%

“…If ECC DIMMs are available, we develop a range of techniques that are based on a two-tiered memory protection approach [33,48,49]. The main innovation of Virtualized ECC is dynamic adaptivity: Virtualized ECC can dynamically map redundant information and vary error protection level based on user or system needs.…”

Section: Introductionmentioning

confidence: 99%

Virtualized and flexible ECC for main memory

Yoon

Erez

2010

SIGPLAN Not.

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We present a general scheme for virtualizing main memory errorcorrection mechanisms, which map redundant information needed to correct errors into the memory namespace itself. We rely on this basic idea, which increases flexibility to increase error protection capabilities, improve power efficiency, and reduce system cost; with only small performance overheads. We augment the virtual memory system architecture to detach the physical mapping of data from the physical mapping of its associated ECC information. We then use this mechanism to develop two-tiered error protection techniques that separate the process of detecting errors from the rare need to also correct errors, and thus save energy. We describe how to provide strong chipkill and double-chip kill protection using existing DRAM and packaging technology. We show how to maintain access granularity and redundancy overheads, even when using ×8 DRAM chips. We also evaluate error correction for systems that do not use ECC DIMMs. Overall, analysis of demanding SPEC CPU 2006 and PARSEC benchmarks indicates that performance overhead is only 1% with ECC DIMMs and less than 10% using standard Non-ECC DIMM configurations, that DRAM power savings can be as high as 27%, and that the system energy-delay product is improved by 12% on average.

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“…Prior works [50,118,51,112,111] have studied cache error protection for uncompressed caches. Kim and Somani [50] propose to only protect the most frequently accessed data as they would propagate errors to other components more easily.…”

Section: Related Workmentioning

confidence: 99%

“…The most recent studies propose to decouple error detection and error correction to minimize the overhead in tolerating errors [112,111]. They propose to keep the light-weight EDC in on-chip cache while offloading the high-cost ECC code to remote off-chip DRAMs given the observation that error correction is a rare event.…”

Section: Related Workmentioning

confidence: 99%

Energy-efficient and cost-effective reliability design in memory systems

Chen¹

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Flexible cache error protection using an ECC FIFO

Cited by 25 publications

References 30 publications

Compiler-assisted detection of transient memory errors

Compiler-assisted detection of transient memory errors

Virtualized and flexible ECC for main memory

Energy-efficient and cost-effective reliability design in memory systems

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