Flexible non-binary LDPC decoding on FPGAs

Andrade, Juliane; Falcão, Gabriel; Silva, Vítor; Kasai, Kazuhiko

doi:10.1109/icassp.2014.6853936

Cited by 11 publications

(6 citation statements)

References 15 publications

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“…Andrade et al used OpenCL in [91] to provide a parallel FFT-SPA decoder architecture suited to the characteristics of a wide-pipeline accelerator, reaching 3.36 Mbps. Later, for the same algorithm, the authors showed that using high-level synthesis (HLS) can reduce the development effort compared to register transfer level (RTL), while they were still able to achieve 14.54 Mbps for 14 cores.…”

Section: B Fpgamentioning

confidence: 99%

“…The implementations missing SNR and the number of iterations [63], [91], [93], [96] do not provide a meaningful contribution in terms of error-correction performance and, alternatively, they focus on resource requirement. In particular, the first decoder implementations [63], [93], [96] pioneered in the analysis of memory requirements for NB-LDPC decoders.…”

Section: ) Analysismentioning

confidence: 99%

“…These designs achieve a throughput performance of less than 2 Mbps except for [94]. The designs from [91] are the largest decoders and occupy more than 300K ELBs per core. In [63], [92], [95], the solutions achieve less resource utilization.…”

Section: B Fpgamentioning

confidence: 99%

“…Designs using FFT-SPA in [91], [92] and AMSA in [105] consume a great deal of resources. Log and mixed domain SPA shows a resource utilization below the trend line [63], [93]- [95], [134].…”

Section: B Fpgamentioning

confidence: 99%

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A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures

Ferraz

Subramaniyan

Ramesh

et al. 2022

IEEE Commun. Surv. Tutorials

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Non-binary low-density parity-check (NB-LDPC) codes show higher error-correcting performance than binary low-density parity-check (LDPC) codes when the codeword length is moderate and/or the channel has bursts of errors. The need for high-speed decoders for future digital communications led to the investigation of optimized NB-LDPC decoding algorithms and efficient implementations that target high throughput and low energy consumption levels. We carried out a comprehensive survey of existing NB-LDPC decoding hardware that targets the optimization of these parameters. Even though existing NB-LDPC decoders are optimized with respect to computational complexity and memory requirements, they still lag behind their binary counterparts in terms of throughput, power and area optimization. This study contributes to an overall understanding of the state-of-the-art on application-specific integrated-circuit (ASIC), field-programmable gate array (FPGA) and Manuscript

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Section: B Fpgamentioning

confidence: 99%

Section: ) Analysismentioning

confidence: 99%

Section: B Fpgamentioning

confidence: 99%

Section: B Fpgamentioning

confidence: 99%

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A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures

Ferraz

Subramaniyan

Ramesh

et al. 2022

IEEE Commun. Surv. Tutorials

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“…The LDPC decoder architecture, based on the FFT-SPA [3], is structured into different kernels composed of double-to triple-nested loop body functions. The optimizations carried out consist of (1) moving all intermediate results from DRAM computation to BRAMdefined arrays; (2) array partitioning to expose more R/W ports and increase bandwidth; (3) unrolling of the innermost loops; and (4) pipelining of the outermost loops.…”

Section: Hls-generated Architecturementioning

confidence: 99%

Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders

Andrade

George

Karras

et al. 2015

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines

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Computing on field-programmable gate arrays (FPGAs) has been receiving continued interest as it provides high performance at relatively low power budgets, while avoiding the high non-recurring engineering (NRE) costs associated with ASIC designs. However, FPGA development is typically performed using register transfer level (RTL) languages which make the design process protracted and error-prone when compared to software design flows. To ease these problems, high-level synthesis (HLS) tools have been introduced which abstract away the RTL architecture description from the designer. In this work we explore the design space of a nonbinary GF(q) low-density parity-check (LDPC) decoder using Vivado HLS and compare it with state-of-the-art RTL designs.

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