Flexible router architecture for network-on-chip

Sayed, Mohamed A.; Shalaby, Ahmed; El-Sayed, Mohamed; Goulart, Victor

doi:10.1016/j.camwa.2012.03.074

Cited by 28 publications

(13 citation statements)

References 8 publications

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“…Hence, the packets are received in order at the destinations contrary to Flexible router in (Sayed et al 2012). NoCs in (Michelogiannakis & Dally 2013;Di Tomaso et al 2012;Ramanujam et al 2011;Jafari et al 2010;Sayed et al 2012) avoid HoL blocking with the help of virtual channels, but this issue is not addressed in the proposed work. Optimized regulator (Jafari et al 2010) avoids IP stalling with the help of additional buffer in between source IP and interconnect.…”

Section: Related Workmentioning

confidence: 98%

“…The optimization is application specific and hence adaptability for different applications is limited. Flexible router (Sayed et al 2012) allows to share the input channel buffers by the packets and hence avoids VCs. But this NoC suffers from out of order reception of packets at destinations.…”

Section: Related Workmentioning

confidence: 99%

“…As a result, this work gains performance, power and area efficiency. Regular NoC topologies with a dimension order routing scheme are considered in (Michelogiannakis et al 2009;Michelogiannakis & Dally 2013;DiTomaso et al 2012;Ramanujam et al 2011;Jafari et al 2010;Sayed et al 2012). In MPSoCs, the use of oversized IPs makes the topology irregular and it requires adaptive fault tolerant routing scheme to provide reliable communication.…”

Section: Related Workmentioning

confidence: 99%

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Runtime buffer management to improve the performance in irregular Network-on-Chip architecture

Umamaheswari

Meganathan

J³

2015

Sadhana

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This paper presents a heterogeneous adaptable router to reduce latency in irregular mesh Network-on-Chip (NoC) architectures. Regular mesh-based NoC architecture may become irregular due to variable sized IPs and needs new routing algorithms to ensure throughput. Therefore, an irregular NoC mesh is considered and an adaptive algorithm is used for routing. The performance measures such as throughput, latency, and bandwidth are defined at design time to guarantee the performance of NoC. However, if the application has to change its communication pattern, parameters set at design time (say buffer size) may result in large area and power consumption or increased latency. Routers with large input buffers improve the efficiency of NoC communication, but they incur excessive power dissipation and hardware overheads. Routers with small buffers reduce power consumption, but result in high latency. In the proposed NoC router, input buffers can be dynamically allocated, thereby, latency can be reduced. In a 4 × 4 irregular mesh NoC with a buffer depth of 4 slots, 20% reduction in latency and 9% increase in throughput are attained using dynamic buffer allocation. An 8 × 8 irregular mesh NoC with the proposed router is exposed to the synthetic traffics like uniform, bit complement, tornado and hotspot traffics and it offered a 30.42% reduction in overall average latency and 18.33% increase in overall saturation throughput. The proposed router outperformed the static router by 22.63% less average latency for E3S benchmark applications. For the same performance, maximum of 55% reduction in buffer requirement and 53% less power consumption is achieved.

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Section: Related Workmentioning

confidence: 98%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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Runtime buffer management to improve the performance in irregular Network-on-Chip architecture

Umamaheswari

Meganathan

J³

2015

Sadhana

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“…However, if the router has a small FIFO depth, the latency will be larger and the quality of service (QoS) can be compromised. The solution is to have a heterogeneous router, [18] in which each channel can have a different buffer size. In this situation, if a channel has a communication rate smaller than its neighbour, it may lend some of its buffer slots that are not being used as explained clearly in stages in the figure 3.…”

Section: Reconfigurable Routermentioning

confidence: 99%

Design of Priority Based Reconfigurable Router in Network on Chip

2020

Informacije MIDEM

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Network on Chip (NoC) is an advanced integration design for communication networks while providing a solution to the traditional bus based System on Chip designs (SoC) too. A router is a key component which is considered as the backbone of communication in NoC. The objective of this work is to design a priority based reconfigurable router for NoC. Initially, a 4x4 Baseline router is designed and synthesised and then the channels inside the router are modified to achieve reconfiguration to improve the router's efficiency. In 4x4 Reconfigurable Router the slots are well utilized but prioritization portion is not considered. Routers are associated with switches to take data transfer decisions resulting in high power consumption. In order to overcome this problem, a new priority based reconfigurable router is designed. The design for this router is carried out using Verilog HDL and synthesized and simulated using Xilinx ISE Design Suite 14.3 and ModelSim-Altera 6.5b Software respectively. The corresponding results in terms of power, energy efficiency, area and delay are analysed and the proposed work gives better results than the conventional Baseline Router. Dizajn prioritetno nastavljivega usmerjevalnika v omrežju na čipuIzvleček: Omrežkje na čipu (NoC) je napredna integracija komunikacijskih omrežij z uporabo tradicionalnih sitemov na čipu na osnovi vodil (SoC). Usmerjevalnik predstavlja ključno komponento v komunikaciji preko NoC. Namen dela je razvoj prioritetno nastavljivega usmerjevalnika za NoC. V osnovi je uporabljen 4x4 usmerjevalnik, v kateremu so, za doseganje učinkovitosti, kanali naknadno razširjeni.Reže v nastavljivem usmerjevalniku so dobro uporabljene, vendar ne upoštevajo prioritet. Usmerjevalniki so povezani s stikali za prenos podatkov, ki imajo visoko porabo. Nastavljivi usmrjevalniku rešujejo problem visoke porabe. Dizajn usmerjevalnika je realiziran v Verilog HDL okolju in simuliran z Xilinx ISE Design Suite 14.3 in ModelSim-Altera 5.5b programsko opremo. Rezultati izkazujejo boljšo učinkovitost, nižjo porabo in zakasnitev predlaganega usmerjevalnika.

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“…Low-power and energy-efficient design is one of the main essential requirements of current and emerging NoC-based systems but it trades-off latency, throughput, and area. [31][32][33][34][35] Like all integrated circuits, FPGAs dissipate static and dynamic power. Static power consumption is the power consumed by a device when it is not clocked and there is no circuit activity (all inputs are stable).…”

mentioning

confidence: 99%

A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip

Alaei

Yazdanpanah

2020

Concurrency and Computation

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High performance system-on-chip (SoCs) designs have led to high-density integrated circuits using field programmable gate arrays (FPGAs) for rapid prototyping and reconfigurable digital circuits. Using FPGA reconfigurability, it is possible to design a configurable network-on-chip (NoC) for different applications. NoC architectures provide efficient communication infrastructures for implementing very large SoCs. In this article, we propose HiFMP, a high-performance FPGA-based multicrossbar prioritized NoC router. The aim followed by the proposed router is designing a low-power NoC router with high performance in terms of energy-efficiency, network throughput, area, and latency for efficient FPGA realization. HiFMP is a parameterizable router, and is effectively used for an FPGA-based NoC with mesh topology. Performance evaluations include network-level analysis and hardware exploration; the results demonstrate the effectiveness and high performance of HiFMP in terms of latency, throughput, power consumption, and area, comparing with the existing related architectures. K E Y W O R D S FPGA, low-power design, multicrossbar, network-on-chip, priority-based router 1 INTRODUCTION In high-density emerging SoC architectures, there are a large number of processing elements (PEs) communicating through intensive on-chip interconnections that significantly affect different aspects of the performance. For large SoCs, point-to-point and bus-based interconnections do not provide efficient on-chip network infrastructures because of large amount of hardware, high latency, high power consumption, and/or complicated synchronization. NoCs, as high-performance architectures, arise to overcome the limitations of traditional on-chip structures. 1-5 NoCs provide high-performance and power scalable and modular interconnections. In addition, with NoC architectures, the system complexity is reduced by separating communication and computation units. A NoC includes routers, links, and network interfaces in order to prepare a network infrastructure for interconnecting PEs. Links of NoCs consist of physical channels (i.e., a group of wires), and optional virtual channels (VCs) as a set of additional buffers in routers. 4-7 The channel bit-width (the number of wires in a unidirectional channel) depends on the bandwidth requirements of the applications and available chip area. Generally, links of NoC have two physical unidirectional channels for fully duplexed communication, allowing data to flow both ways without collisions. 1 Routers are the most important modules of the communication backbone of NoC architectures. So, it is essential to design them with low latency, low power consumption, and high throughput. The router complexity and performance impacts the latency, power consumption, area, throughput, and the cost of on-chip networks. 8 Field programmable gate arrays (FPGAs) are flexible, easy-to-use, and cost effective reprogrammable devices with fast and simple design flow. FPGA designers generally do not need to care for clock distribut...

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Flexible router architecture for network-on-chip

Cited by 28 publications

References 8 publications

Runtime buffer management to improve the performance in irregular Network-on-Chip architecture

Runtime buffer management to improve the performance in irregular Network-on-Chip architecture

Design of Priority Based Reconfigurable Router in Network on Chip

A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip

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