Flip-chip assembly for photonic circuits

Wörhoff, Kerstin; Heideman, René; Gilde, M.J.; Blidegn, Kristian; Heschel, M.; Vlekkert, Hans van den

doi:10.1117/12.545952

Cited by 3 publications

(3 citation statements)

References 2 publications

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“…However, thermo-compression is also not an ideal solution, because it suffers from poorer chip-to-chip alignment tolerances than solder-reflow, and is a more complicated process to implement. Several solutions for flux-free solder-reflow bonding have been proposed, including (i) laser induced flipchip bonding using an In and Ag nano-particle based ink [14], (ii) Au-Sn solder which is relatively free from oxidation [9], (iii) wafer-level bonding in a vacuum chamber [15], and (iv) solderreflow in a forming-gas (i.e., H 2 buffered in N 2 ) to help decompose the oxides [16]. These novel approaches have not been widely implemented, because they are difficult to merge with established industrial flip-chip bonding production-lines, and require relatively costly modifications to the manufacturing infrastructure.…”

Section: Electronic-photonic Integrationmentioning

confidence: 99%

“…Driven by the economic pressure of reducing chip-footprints, and the need for more-and-more electronic interconnects to increase device functionality and speed, there is a constant push to reduce the pitch of the connections between the PIC and the electronic-IC. For conventional solder-ball-bumps (SBBs), the interconnect pitch is limited to approximately 50-100 μm [9], which gives an interconnect density on the order of 200 mm −2 . Copper-pillar-bump (CPB) interconnects have recently been proposed for high-density electronic-photonic integration, because they offer an even lower pitch and better RFand thermal-coupling between the PIC and electronic-IC [10].…”

Section: Introductionmentioning

confidence: 99%

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Meeting the Electrical, Optical, and Thermal Design Challenges of Photonic-Packaging

Lee¹,

Carroll²,

Scarcella³

et al. 2016

IEEE J. Select. Topics Quantum Electron.

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Integrated photonics is a promising route toward high-performance next-generation ICT and sensing devices. Although fiber-packaging is perhaps the most widely discussed obstacle to low-cost photonic devices, electronic-photonic integration and thermal-stabilization are also significant design considerations that need to be properly managed. Using a state-of-the-art Si-photonic optical-network-unit as a worked example, we illustrate some key challenges and solutions in the field of photonicpackaging. Specifically, we describe a novel solder-reflow bonding process for the face-to-face three-dimensional (3-D) integration of photonic and electronic integrated circuits, discuss current and future multichannel fiber-alignment techniques, and investigate the coefficient-of-performance of the thermo-electric cooler that stabilizes the temperature of the photonic components. The challenge of photonic-packaging is to simultaneously satisfy these electrical, optical, and thermal design requirements on small-footprint devices, while establishing a route to scalable commercial implementation.

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Section: Electronic-photonic Integrationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Meeting the Electrical, Optical, and Thermal Design Challenges of Photonic-Packaging

Lee¹,

Carroll²,

Scarcella³

et al. 2016

IEEE J. Select. Topics Quantum Electron.

View full text Add to dashboard Cite

show abstract

“…The vertical integration of an EIC on a PIC can be made using either solder-ball-bump (SBBs) or copper-pillar-bump (CPBs) interconnects, which provide an electrical, mechanical, and thermal interface between the two chips [46,47]. In particular, vertical integration improves the high-speed electronic interface to the PIC, because it acts to replace long (100-500 µm) possibly curved, wire-bonds with short (≈10 µm) SBB or CPB interconnects, which minimizes parasitic induction effects [48][49][50]-see Figure 12.…”

Section: Vertical Integrationmentioning

confidence: 99%

Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices

et al. 2016

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Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved.

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Recent progress in quantum photonic chips for quantum communication and internet

et al. 2023

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Recent years have witnessed significant progress in quantum communication and quantum internet with the emerging quantum photonic chips, whose characteristics of scalability, stability, and low cost, flourish and open up new possibilities in miniaturized footprints. Here, we provide an overview of the advances in quantum photonic chips for quantum communication, beginning with a summary of the prevalent photonic integrated fabrication platforms and key components for integrated quantum communication systems. We then discuss a range of quantum communication applications, such as quantum key distribution and quantum teleportation. Finally, the review culminates with a perspective on challenges towards high-performance chip-based quantum communication, as well as a glimpse into future opportunities for integrated quantum networks.

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Flip-chip assembly for photonic circuits

Cited by 3 publications

References 2 publications

Meeting the Electrical, Optical, and Thermal Design Challenges of Photonic-Packaging

Meeting the Electrical, Optical, and Thermal Design Challenges of Photonic-Packaging

Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices

Recent progress in quantum photonic chips for quantum communication and internet

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