Flip chip power MOSFET: a new wafer scale packaging technique

Arzumanyan, A.M.; Sodhi, R.; Kinzer, D.; Schofield, Helen; Sammon, T.

doi:10.1109/ispsd.2001.934602

Cited by 4 publications

(1 citation statement)

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“…Today, with some exceptions, power packages require some kind of 'loop' interconnect from the upper side of the die to the bottom side of the package [7]. This is the case for standard TO-XXX packages, PQFN packages, but also for proprietary and wire bond free package designs, some of which use a metal can (large cross-section) to efficiently form that loop from the topside of the die down to the PCB [8,9,10].…”

Section: Interconnect Resistance and Modelingmentioning

confidence: 99%

Ribbon Bonding - A Scalable Interconnect for Power QFN Packages

Luechinger

2007

2007 9th Electronics Packaging Technology Conference

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Continuous improvements in Silicon technology enable an ongoing reduction in Silicon-intrinsic on-state resistance, especially for low voltage MOSFETs, or shrinking the die size for a given on-state resistance. At the same time, new features and functionality create a need for power packages that more efficiently use the available space in many end applications. Smaller packages and multi-chip packages save system space and require less packaging material, both of which are main cost factors.The Power Quad Flat-Pack No-Lead (PQFN) package design appears to be the most promising standard package design to support these needs for improved performance, smaller size, and lower cost. But none of the interconnect techniques established in the existing power package families, like TO-XXX and power SO-XX, large Aluminum (Al) wire bonding, fine wire Gold (Au) and Copper (Cu) ball bonding, or Cu clip/strap bonding, will allow covering the complete spectrum of PQFN package sizes effectively.This paper describes the ribbon interconnect design and its characteristics. It demonstrates its effectiveness over the complete range of PQFN package sizes from 2x2mm to 12x12mm, for present and future Silicon performance levels. Interconnect resistance calculations are used to compare different configurations and deduce design recommendations. The results of the study point to ribbon bonding as the most effective standard power interconnect technique, especially considering the trend towards decreasing die and package sizes, and indicate a good fit with the PQFN package concept. IntroductionToday TO-XXX and SO-XX type packages still represent by far the largest percentage of power packages that are produced. TO-type packages are used where size is not critical, but power capability is most important. SO-8 packages, especially, are the standard package for lower power applications, but often also applications with reduced reliability requirements and limited availability of space. These packages follow common standards and are produced on standard assembly equipment at many locations and by suppliers with limited opportunities for differentiation except price. Standardization was the enabler of this situation, and was therefore a key factor for the low manufacturing cost. But both package designs, TO-XXX and SO-XX, have limitations towards addressing future power packaging needs.For some time the need for reduced package size and improved performance of discrete power semiconductors was approached with novel power package designs, most of which also intended to eliminate wire bonding as the topside die to package interconnect [1]. Many of those designs indeed enable improved performance at reduced package size, but often at significantly increased cost, caused by their complex design, which often requires special materials and/or assembly processes and equipment. Non-mainstream or even proprietary designs often allow only single or limited sourcing. That limits competition and prevents economies of scale, two powerful enablers of cost r...

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Section: Interconnect Resistance and Modelingmentioning

confidence: 99%