Flip chip underfill flow characteristics and prediction

Fine, P.; Cobb, B.; Nguyen, Luu

doi:10.1109/ectc.1999.776272

Cited by 10 publications

(2 citation statements)

References 3 publications

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“…Void formation is often induced by irregular underfill flow fronts in silicon dies containing non-uniform bump patterns or the edge effect where the underfill flow along die edges advances faster than that in the middle of the die due to a larger bump resistance at the chip inner core [2,3]. With the continuous increase of I/O counts in flip-chip packages, higher bump density and finer pitch size result in longer underfill flow-out time and more voids formed during underfill encapsulation.…”

Section: Introductionmentioning

confidence: 99%

A multiscale modeling and experimental study of underfill flow and void formation for flip-chip packages

Zhou

Sun

Libres

et al. 2009

2009 59th Electronic Components and Technology Conference

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This paper uses a validated, two-dimensional global underfill flow model previously developed by the authors [1] to examine the effects of substrate surface (ceramic vs. organic) and temperature-dependent underfill viscosity on underfill flow-out time, flow front shape, and void formation during the flip chip encapsulation process. Model predictions are validated by experiments using bumped quartz dies that allow for direct visualization of the underfill infiltration process. In addition, a full three-dimensional underfill flow model is developed to quantify the effect of slanted and convex-shaped solder bumps. The filler particle inhomogeneity due to settling and shear migration is also accounted for in the model. The present study seeks to provide a comprehensive understanding of concurrent effects in the flip-chip underfilling process.978-1-4244-4476-2/09/$25.00

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Section: Introductionmentioning

confidence: 99%

A multiscale modeling and experimental study of underfill flow and void formation for flip-chip packages

Zhou

Sun

Libres

et al. 2009

2009 59th Electronic Components and Technology Conference

View full text Add to dashboard Cite

show abstract

“…It enhances the reliability performance of the flip chip package. The die size, bump pitch, and stand off height of the package are among the important parameters can affect the underfill flow (4)(5)(6)(7)(8)(9)(10)(11). The presence of flux residue and substrate wettability can also affect underfill flow (12)(13)(14)(15).…”

Section: Introductionmentioning

confidence: 99%

The Effect of Flux Residue and Substrate Wettability on Underfill Flow Process in Flip-Chip Packages

Wang

56th Electronic Components and Technology Conference 2006

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The surface energies of different substrates and wetting angles of fluxes on the substrates were measured and showed differences between different substrates. The viscosity of fluxes at low stress shows a good correlation with their wetting properties. The modulus of flux residue varies significantly between different fluxes and high modulus flux residue is difficult to remove. The correlation between underfill, substrate properties, and underfill flow voids will be discussed. An underfill flow study with quartz die packages was conducted. The effect of flux residue and substrate wetting properties were assessed by this underfill flow study. This study will help us in minimizing the flux residue effect on underfill flow and optimizing underfill flow process.

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Evaluating underfill materials for high reliability applications

Goodelle¹,

Gilbert²,

Fanucci³

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)

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Flip chip underfill flow characteristics and prediction

Cited by 10 publications

References 3 publications

A multiscale modeling and experimental study of underfill flow and void formation for flip-chip packages

A multiscale modeling and experimental study of underfill flow and void formation for flip-chip packages

The Effect of Flux Residue and Substrate Wettability on Underfill Flow Process in Flip-Chip Packages

Evaluating underfill materials for high reliability applications

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