Float-to-fixed and fixed-to-float hardware converters for rapid hardware/software partitioning of floating point software applications to static and dynamic fixed point coprocessors

Saldanha, Lance; Lysecky, Roman

doi:10.1007/s10617-009-9044-4

Cited by 7 publications

(4 citation statements)

References 25 publications

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“…In all three architectures, we conservatively use 64-bit fixed-point numbers, with 32 bits for the fractional part. Since the data available from ECMWF models is in floatingpoint, we instantiate a floating-point to fixed-point converter in the FPGA for dynamic conversions in all three cases [8]. The slice usage and calculation latency estimates are shown for Virtex-5 XC5VLX devices.…”

Section: Design Considerationsmentioning

confidence: 99%

A Reconfigurable Vector Instruction Processor for Accelerating a Convection Parametrization Model on FPGAs

Nabi,

Hameed,

Vanderbauwhede

2015

Preprint

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High Performance Computing (HPC) platforms allow scientists to model computationally intensive algorithms. HPC clusters increasingly use General-Purpose Graphics Processing Units (GPGPUs) as accelerators; FPGAs provide an attractive alternative to GPGPUs for use as co-processors, but they are still far from being mainstream due to a number of challenges faced when using FPGA-based platforms. Our research aims to make FPGA-based high performance computing more accessible to the scientific community. In this work we present the results of investigating the acceleration of a particular atmospheric model, Flexpart, on FPGAs. We focus on accelerating the most computationally intensive kernel from this model. The key contribution of our work is the architectural exploration we undertook to arrive at a solution that best exploits the parallelism available in the legacy code, and is also convenient to program, so that eventually the compilation of high-level legacy code to our architecture can be fully automated. We present the three different types of architecture, comparing their resource utilization and performance, and propose that an architecture where there are a number of computational cores, each built along the lines of a vector instruction processor, works best in this particular scenario, and is a promising candidate for a generic FPGA-based platform for scientific computation. We also present the results of experiments done with various configuration parameters of the proposed architecture, to show its utility in adapting to a range of scientific applications.

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Section: Design Considerationsmentioning

confidence: 99%

A Reconfigurable Vector Instruction Processor for Accelerating a Convection Parametrization Model on FPGAs

Nabi,

Hameed,

Vanderbauwhede

2015

Preprint

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“…Most embedded systems, System-on-Chip (SoC) and transmission systems are implemented using either fixed point, floating point or hybrid number systems wherein fixed [1] [2] and floating point numbers [3] [4] can be used together in the same chip [5]- [7]. The IEEE754-1985 standard was released for binary floating point arithmetic with some new features such as better precision, range and accuracy [8].…”

Section: Introductionmentioning

confidence: 99%

“…The numbers that are used in many DSP and communication systems are scaled between [−1, 1). The [−1, 1) scaled version of equations (3) and (4) can be written as Equations (5) and (6)…”

Section: Introductionmentioning

confidence: 99%

Open Source Synthesis and Verification Tool for Fixed-to-Floating and Floating-to-Fixed Points Conversions

Aslan¹,

Mohammad²,

Salamy³

2016

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An open source high level synthesis fixed-to-floating and floating-to-fixed conversion tool is presented for embedded design, communication systems, and signal processing applications. Many systems use a fixed point number system. Fixed point numbers often need to be converted to floating point numbers for higher accuracy, dynamic range, fixed-length transmission limitations or end user requirements. A similar conversion system is needed to convert floating point numbers to fixed point numbers due to the advantages that fixed point numbers offer when compared with floating point number systems, such as compact hardware, reduced verification time and design effort. The latest embedded and SoC designs use both number systems together to improve accuracy or reduce required hardware in the same design. The proposed open source design and verification tool converts fixed point numbers to floating point numbers, and floating point numbers to fixed point numbers using the IEEE-754 floating point number standard. This open source design tool generates HDL code and its test bench that can be implemented in FPGA and VLSI systems. The design can be compiled and simulated using open source Iverilog/GTKWave and verified using Octave. A high level synthesis tool and GUI are designed using C#. The proposed design tool can increase productivity by reducing the design and verification time, as well as reduce the development cost due to the open source nature of the design tool. The proposed design tool can be used as a standalone block generator or implemented into current designs to improve range, accuracy, and reduce the development cost. The generated design has been implemented on Xilinx FPGAs.

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“…Biasing is pipelined and performed in 4 cycles. The inverse process (unbiasing) requires an 8-bit addition to all decompressed values and requires one cycle.Float to fixed & fixed to float conversions: Converting from float to fixed point numbers and vice-versa is implemented as described in[35] requiring a single cycle.…”

mentioning

confidence: 99%

Avr

Eldstål-Damlin

Trancoso

Sourdis

2019

Proceedings of the 48th International Conference on Parallel Processing

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This paper describes Approximate Value Reconstruction (AVR), an architecture for approximate memory compression. AVR reduces the memory traffic of applications that tolerate approximations in their dataset. Thereby, it utilizes more efficiently the available off-chip bandwidth improving significantly system performance and energy efficiency. AVR compresses memory blocks using low latency downsampling that exploits similarities between neighboring values and achieves aggressive compression ratios, up to 16:1 in our implementation. The proposed AVR architecture supports our compression scheme maximizing its effect and minimizing its overheads by (i) co-locating in the Last Level Cache (LLC) compressed and uncompressed data, (ii) efficiently handling LLC evictions, (iii) keeping track of badly compressed memory blocks, and (iv) avoiding LLC pollution with unwanted decompressed data. For applications that tolerate aggressive approximation in large fractions of their data, AVR reduces memory traffic by up to 70%, execution time by up to 55%, and energy costs by up to 20% introducing up to 1.2% error to the application output. CCS CONCEPTS • Computer systems organization → Other architectures; • Hardware → Memory and dense storage.

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Float-to-fixed and fixed-to-float hardware converters for rapid hardware/software partitioning of floating point software applications to static and dynamic fixed point coprocessors

Cited by 7 publications

References 25 publications

A Reconfigurable Vector Instruction Processor for Accelerating a Convection Parametrization Model on FPGAs

A Reconfigurable Vector Instruction Processor for Accelerating a Convection Parametrization Model on FPGAs

Open Source Synthesis and Verification Tool for Fixed-to-Floating and Floating-to-Fixed Points Conversions

Avr

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