Floating gate potential of gate-all-around floating gate memory cell: parameter extraction and compact model

Abstract

The compact modeling of NAND flash memories is crucial for integrated circuit designers to carry out efficient and precise circuit-level evaluations, particularly in the case of 3D NAND flash where the 3D geometry leads to significant parasitic coupling impacts on performance. In this work, we proposed a charge-based modeling approach for gate-all-around floating gate memory cells. The compact model is based on the derived unified charge control model where the mobile charge is explicitly solved. By solving the charge balance model and taking into account voltage-dependent parasitic capacitances for accurate coupling effects, the floating gate potential is accurately computed. The simulation results are validated with numerical TCAD simulation and showed good agreement with TCAD simulation. By solving the charge balance model and considering voltage-dependent parasitic capacitances for more accurate coupling effects, the floating gate potential is accurately calculated. The simulation results were validated using numerical TCAD simulation and showed good agreement, demonstrating that the floating gate potential is accurately estimated through the inclusion of voltage-dependent parasitic capacitances. Additionally, the results indicate that subthreshold degradation is caused by interface trap charge in the experimental device, and the proposed model successfully replicates experimental data.