Floorplanner for multi-core micro-processors in 3D ICs with interlayer cooling system

Abstract

3D ICs is a solution for multi-core processors, with critical challenge of internal thermal problem. A new solution for this problem is interlayer cooling system, which expands the floorplan design space of micro-processors in 3D ICs. This work proposes a floorplanner for multicore processor in 3D ICs with interlayer cooling system, integrated with greedy and particle swarm optimization method. The results show that the maximal temperature and temperature gradient reduced by 10.3°C and 9.2°C respectively, compared with the baseline design in 3 active device layers.

Thermal placement on PCB of components including 3D ICs

“…Thermal-aware 3D network-on-chip (NoC) designs have been proposed [10,11]. Related to the thermal placement of 3D ICs, thermal through-silicon-via (TSV) optimization [12,13,14,15,16] and thermal floor plans [17,18,19,20,21,22,23,24,25,26] have been presented. Placement optimization of chips in SoP designs has been presented [27].…”