Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs

Zhou, Qiang; Shi, Jin; Liu, Bin; Cai, Yici

doi:10.1109/tvlsi.2009.2037428

Cited by 15 publications

(29 citation statements)

References 17 publications

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“…The optimization methods proposed in [2] and [3] reduce the IR-drop by adjusting power straps such as changing the place of power straps, increasing the density of power straps where current noise is high, and amplifying the power strap area. However, the excess power straps lead to serious placement and routing problem for chips.…”

Section: Previous Workmentioning

confidence: 99%

IGS: The Novel Fast IC Power Ground Network Optimization Flow Based on Improved Gauss-Seidel Method

Ye¹,

Wang²,

Gong³

et al. 2017

Adv. sci. technol. eng. syst. j.

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Section: Previous Workmentioning

confidence: 99%

IGS: The Novel Fast IC Power Ground Network Optimization Flow Based on Improved Gauss-Seidel Method

Ye¹,

Wang²,

Gong³

et al. 2017

Adv. sci. technol. eng. syst. j.

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“…In this, the designers have a choice of assigning high supply voltage to the critical cells and low supply voltage to noncritical cells. Consequently, it reduces the power and delay in circuits [1]. As the chip has more number of modules, it is essential to have a power planning aware floorplan representation for the placement of modules below their respective power rails.…”

Section: Introductionmentioning

confidence: 99%

“…The equation (1) shows that an increase in current density reduces the MTTF. In [4], Jens Lienig and Göran proposed methods based on verification of current density in interconnect during the physical design process of an IC.…”

Section: Introductionmentioning

confidence: 99%

Analysis of a Multiple Supply Voltage Floorplan Considering Voltage Drop and Electron Migration Risk

Srinath¹,

Priya²,

Kasliwal³

2018

IJET

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In Contemporary Integrated Circuits (IC), the Voltage drop in the power rails and Electron migration risk (EM) due to high current densities are the most important factors degrading the reliability of the chip. The effect of these factors leads to an imbalance in the flow of charge carriers and voids in interconnects. This paper resolves the above issues, through analyzing and predetermining it in a Multiple Supply Voltage (MSV) design during the floorplanning stage. Simulations were carried out in Cadence digital Encounter system with 180nm technology for the circuit net list of 8 point FFT (Fast Fourier Transform) and FIR filter. Results show that floorplanning scheme is powerful in reducing 100% of voltage drop and 50% of EM risk in the chip as compared to previous works.

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“…All blocks inside the island operate at the same voltage and occupy a contiguous physical space, whereas the remaining blocks outside these islands operate at the chip-level voltage. In terms of power/ground (P/G) network, each island has its independent power supply network while the blocks working in chip-level voltage are powered by a global power network [2].…”

Section: Introductionmentioning

confidence: 99%

“…The model is a rough estimation which lacks P/G network details such as power pad locations and P/G network topology. Zhou et al consider the power delivery problem in VI designs during the floorplanning process to reduce the design iterations [2]. They proved that it is unnecessary to find an optimal pitch parameter for P/G network during floorplanning stage and proposed a voltage drop aware floorplanning method with a fixed topology P/G network.…”

Section: Introductionmentioning

confidence: 99%

Voltage Drop Aware Power Pad Assignment and Floorplanning for Multi-voltage SoC Designs

Chu

Xia

Wang

et al. 2013

2013 International Conference on Computer-Aided Design and Computer Graphics

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Multi-voltage technique is an effective way of power saving in system-on-a-chip (SoC) designs. However, as the technology nodes continue to shrink, the voltage drop constraint in multiple power domains presents serious obstacles in power/ground (P/G) network design of wire-bonding package. In this paper, a voltage drop aware power pad assignment and floorplanning method for multi-voltage SoC designs is proposed. In order to reduce the voltage drop, we develop a fast method to calculate the location of power pad for each power domain based on the spring model. During floorplanning iterations, a static voltage drop analysis is performed to update the voltage drop distribution, and then number of violation nodes in the P/G network is obtained. To speed up the floorplanning algorithm, instead of time-consuming matrix computation to obtain voltage drops, we use the weighted distance from blocks to power pads as an optimization objective. Experimental results on GSRC benchmark suites indicate that the proposed approach generates an optimized placement of power pads and floorplanning of blocks.

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Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs

Cited by 15 publications

References 17 publications

IGS: The Novel Fast IC Power Ground Network Optimization Flow Based on Improved Gauss-Seidel Method

IGS: The Novel Fast IC Power Ground Network Optimization Flow Based on Improved Gauss-Seidel Method

Analysis of a Multiple Supply Voltage Floorplan Considering Voltage Drop and Electron Migration Risk

Voltage Drop Aware Power Pad Assignment and Floorplanning for Multi-voltage SoC Designs

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