2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines 2014
DOI: 10.1109/fccm.2014.61
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Floorplanning for Partially-Reconfigurable FPGA Systems via Mixed-Integer Linear Programming

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Cited by 27 publications
(53 citation statements)
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“…To our knowledge, there is no other work that considers the temperature effects in floorplanning, so for comparison purposes we considered a second approach, Thermal Optimal TO, that extends the state-of-the-art floorplanner presented in [9]. In [9] TAF stems from the MILP models presented in [9], it exploits the [HO] formulation in order to obtain a placement of the RRs starting from the sequence pair description. The use of [HO] allows to obtain the optimal solution with respect to the linear components of the objective function and the sequence pair considered at the current iteration of the SA, while the non-linear metrics are optimized by the annealer.…”
Section: Introductionmentioning
confidence: 99%
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“…To our knowledge, there is no other work that considers the temperature effects in floorplanning, so for comparison purposes we considered a second approach, Thermal Optimal TO, that extends the state-of-the-art floorplanner presented in [9]. In [9] TAF stems from the MILP models presented in [9], it exploits the [HO] formulation in order to obtain a placement of the RRs starting from the sequence pair description. The use of [HO] allows to obtain the optimal solution with respect to the linear components of the objective function and the sequence pair considered at the current iteration of the SA, while the non-linear metrics are optimized by the annealer.…”
Section: Introductionmentioning
confidence: 99%
“…In addition, in order to exploit modern FPGA capabilities like Partial Reconfiguration (PR) additional constraints must be taken into account: each region should cover the required amount of heterogeneous resources [2], while having the right shape in order to allow PR [3]. Different solutions have been developed ([4]- [9]), but only few of them ( [4], [5], [9]) deal with the previous constraints.…”
Section: Introductionmentioning
confidence: 99%
“…Within this work, we propose an extension of our previous approach [10] adding support for bitstream relocation for both HO and O algorithm. We first propose a revised FPGA partitioning procedure that eases the extension of the model, then, the MILP model at the core of [10] is enhanced to address both constraints and metrics related to bitstream relocation.…”
Section: Introductionmentioning
confidence: 99%
“…The former, by means of a method called Columnar Kernel Tessellation, meanly focuses on reducing the overall amount of wasted resources to minimize the bitstream size, while the latter, exploits simulated annealing to reduce the overall wire length. On the other hand, the two algorithms presented in [10], based on a MILP formulation, allow to improve the quality of the solutions achieved by [9] and [8] at the cost of a generally higher execution time. The first approach called HO (Heuristic Optimal), extracts the sequence pair representation of a first feasible solution and uses it as an additional constraint to reduce the size of the search space so that the initial solution can be locally improved in a small amount of time.…”
Section: Introductionmentioning
confidence: 99%
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