Floorplanning for Placement of Modules in VLSI Physical Design Using Harmony Search Technique

Karimullah, Shaik; Vardhan, D. Vishnu; Basha, Syed Javeed

doi:10.1007/978-981-15-1420-3_197

Cited by 20 publications

(2 citation statements)

References 2 publications

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“…Finally, it will be necessary to evaluate the adoption of the strategy described in this work in other engineering fields. For instance, the design of Very-Large-Scale Integration (VLSI) circuits commonly faces problems that require the determination of optimal routes between the circuits that interconnect various electronic components, thereby implying the minimization of wiring length [45][46][47][48].…”

Section: Discussionmentioning

confidence: 99%

A Look at Algorithm BEPtoPNST

Ojeda¹

2020

rev.ing.univ.Medellin

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This work analyzes the computational complexity of algorithm BEPtoPNST which transforms a building-evacuation problem (BEP) into a time-ex-panded, process-network synthesis (PNST) problem. The solution of the latter is achieved by resorting to the P-graph method which exploits the combinatorial nature of a BEP. Unlike other approaches, the P-graph method provides not only the optimal solution (best evacuation route as a function of egress time), but also the best n sub-optimal solutions. For the complexity analysis, a generic processor, and a Random-access machine (RAM) model were deployed as well as a mathematical model to calculate the number and cost of the operations performed. It was observed that algorithm BEPtoPNST exhibits an asymptotic complexity of order O ( T | A | (| N | –k)). When solving a BEP, however, the total complexity grows exponentially with order O (T | A | (| N | –k)) + O (2h)) in the worst case; where h represents the total number of operating units specified in the corresponding PNST problem. Nevertheless, the computational comple-xity can be reduced significantly when the P-graph method is deployed.

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Section: Discussionmentioning

confidence: 99%

A Look at Algorithm BEPtoPNST

Ojeda¹

2020

rev.ing.univ.Medellin

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“…e evaluation of the Location and Route Streams of Aware Synthesis is carried out and the result is created. Considering large-scale blended size arrangements, [7] examines an intriguing computation that is based on a heuristic in order to arrive at a convincing conclusion. Four steps must be completed in order for the procedure to be successful: assembling the items into blocks, predicting where the blocks will be placed on a floor, and increasing the wire length for good transport.…”

Section: Review Of Literaturementioning

confidence: 99%

Perimeter Degree Technique for the Reduction of Routing Congestion during Placement in Physical Design of VLSI Circuits

Lakshmanna

Shaik²,

Gunjan³

et al. 2022

Complexity

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When used in conjunction with the current floorplan and the optimization technique in circuit design engineering, this research allows for the evaluation of design parameters that can be used to reduce congestion during integrated circuit fabrication. Testing the multiple alternative consequences of IC design will be extremely beneficial in this situation, as will be demonstrated further below. If the importance of placement and routing congestion concerns is underappreciated, the IC implementation may experience significant nonlinear problems throughout the process as a result of the underappreciation of placement and routing congestion concerns. The use of standard optimization techniques in integrated circuit design is not the most effective strategy when it comes to precisely estimating nonlinear aspects in the design of integrated circuits. To this end, advanced tools such as Xilinx VIVADO and the ICC2 have been developed, in addition to the ICC1 and VIRTUOSO, to explore for computations and recover the actual parameters that are required to design optimal placement and routing for well-organized and ordered physical design. Furthermore, this work employs the perimeter degree technique (PDT) to measure routing congestion in both horizontal and vertical directions for a silicon chip region and then applies the technique to lower the density of superfluous routing (DSR) (PDT). Recently, a metaheuristic approach to computation has increased in favor, particularly in the last two decades. It is a classic graph theory problem, and it is also a common topic in the field of optimization. However, it does not provide correct information about where and how nodes should be put, despite its popularity. Consequently, in conjunction with the optimized floorplan data, the optimized model created by the Improved Harmonic Search Optimization algorithm undergoes testing and investigation in order to estimate the amount of congestion that occurs during the routing process in VLSI circuit design and to minimize the amount of congestion that occurs.

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