Flow control in ATM networks: a survey

Kamolphiwong, Sinchai; Karbowiak, A.E.; Mehrpour, H.

doi:10.1016/s0140-3664(98)00155-8

Cited by 16 publications

(4 citation statements)

References 68 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Unlike in [17], however, careful analysis based on the physical constraints is done for the communication buffer requirements, which will be discussed in detail within the next section. We selected the credit-based scheme due to the advantages presented in [19], [20] such as: it is faster than its rate-based counterparts; there is no data loss if there is any congestion; and data rate can be as high as the full link speed with no data loss, which promises good network resource utilization.…”

Section: Related Workmentioning

confidence: 99%

Scalability Analysis of Deeply Pipelined Tsunami Simulation with Multiple FPGAs

Mondigo

Ueno

Sano

et al. 2019

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

Since the hardware resource of a single FPGA is limited, one idea to scale the performance of FPGA-based HPC applications is to expand the design space with multiple FPGAs. This paper presents a scalable architecture of a deeply pipelined stream computing platform, where available parallelism and inter-FPGA link characteristics are investigated to achieve a scaled performance. For a practical exploration of this vast design space, a performance model is presented and verified with the evaluation of a tsunami simulation application implemented on Intel Arria 10 FPGAs. Finally, scalability analysis is performed, where speedup is achieved when increasing the computing pipeline over multiple FPGAs while maintaining the problem size of computation. Performance is scaled with multiple FP-GAs; however, performance degradation occurs with insufficient available bandwidth and large pipeline overhead brought by inadequate data stream size. Tsunami simulation results show that the highest scaled performance for 8 cascaded Arria 10 FPGAs is achieved with a single pipeline of 5 stream processing elements (SPEs), which obtained a scaled performance of 2.5 TFlops and a parallel efficiency of 98%, indicating the strong scalability of the multi-FPGA stream computing platform.

show abstract

Section: Related Workmentioning

confidence: 99%

Scalability Analysis of Deeply Pipelined Tsunami Simulation with Multiple FPGAs

Mondigo

Ueno

Sano

et al. 2019

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

show abstract

“…As we have said earlier, the number of research activities regarding QoS and ATM networks is huge. Very extensive and interesting reviews can be found on [25]- [26]- [27].…”

Section: Asynchronous Transfer Mode (Atm)mentioning

confidence: 99%

A Survey on QoS in Next Generation Networks

Karam

Jensen²

2010

AISS

View full text Add to dashboard Cite

This paper presents an exhaustive state of the art survey about QoS over heterogeneous networks. With the advent of novel networks technologies, researchers have been working on how to implement and ensure that QoS is achieved in heterogeneous networks. We believe that there have been some improvements, but there is much to do. Additionally, the survey shows the great effort which has been undertaken by the research community in order to address the topic over these years. The blossoming of ideas is plethoric and gives us a notion about the tremendous scope covered by the subject.

show abstract

“…The general idea is to adjust traffic flow into the network in such a way as to optimise network performance. One well-developed rate control scheme is the Explicit Rate Indication with Congestion Avoidance (ERICA) scheme [8]. Under this control scheme, the source monitors its load and periodically sends control cells that contain the load information.…”

Section: Introductionmentioning

confidence: 99%

ATM congestion control using Minimal Resource Allocation Networks (MRAN)

Soon

Sundararajan

Saratchandran

2003

Neural Computing & Applications

View full text Add to dashboard Cite

This paper presents a congestion control scheme for ATM traffic using a minimal radial basis function neural network referred to as Minimal Resource Allocation Network (MRAN). Earlier studies have shown that MRAN is well suited for online adaptive control of nonlinear time varying systems as it can adjust its size by adding and pruning the hidden neurons based on the input data. Since ATM traffic is nonlinear and time varying performance of MRAN as a congestion controller is investigated here. These studies are carried out using OPNET to model the ATM traffic. The ATM traffic model consists of bursty, Variable BitRate (VBR) and custom traffic in a multiplexed form so as to generate a heavily congested traffic situation. For this scenario, the controller has to minimize the congestion episodes and maintain the Quality of Service (QoS) requirements. This paper compares the performance of the MRAN congestion controller with that of a modified Explicit Rate Indication with Congestion Avoidance (ERICA) scheme and a Back-Propagation (BP) neural controller. Simulation results indicate that MRAN controller performs better than the modified ERICA and BP controller in reducing the congestion episodes and maintaining the desirable QoS.

show abstract

Flow control in ATM networks: a survey

Cited by 16 publications

References 68 publications

Scalability Analysis of Deeply Pipelined Tsunami Simulation with Multiple FPGAs

Scalability Analysis of Deeply Pipelined Tsunami Simulation with Multiple FPGAs

A Survey on QoS in Next Generation Networks

ATM congestion control using Minimal Resource Allocation Networks (MRAN)

Contact Info

Product

Resources

About