FlowGNN: A Dataflow Architecture for Real-Time Workload-Agnostic Graph Neural Network Inference

Sarkar, Rishov; Stefan, Abi-Karam,; He, Yuan; Sathidevi, Lakshmi; Hao, Cong

doi:10.1109/hpca56546.2023.10071015

Cited by 36 publications

(8 citation statements)

References 38 publications

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“…First, we manually translate the sPHENIX model into synthesizable C code and feed it into the HLS tool, Vitis HLS [6]. Then, we perform hardware optimizations of the model in HLS following the FlowGNN architecture [7], which is the state-of-the-art GNN architecture on FPGA.…”

Section: Generation Of the Gnn Ip Corementioning

confidence: 99%

“…The current TrackGNN model in sPHENIX we are using has one GNN layer, which includes 4 multi-layer perceptron (MLP) layers for both node and edge embedding with a dimension of 8. The proposed architecture follows the message-passing framework in FlowGNN [7]: the node embeddings are processed first, followed by an adapter to orchestrate the node information to the correct edge processing units for edge embedding computation and message aggregation. We also use quantization to reduce the data precision and to reduce the memory and computation requirements.…”

Section: Generation Of the Gnn Ip Corementioning

confidence: 99%

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A demonstrator for a real-time AI-FPGA-based triggering system for sPHENIX at RHIC

Kvapil,

Borca-Tasciuc,

Bossi

et al. 2024

J. Inst.

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The RHIC interaction rate at sPHENIX will reach around 3 MHz in pp collisions and requires the detector readout to reject events by a factor of over 200 to fit the DAQ bandwidth of 15 kHz. Some critical measurements, such as heavy flavor production in pp collisions, often require the analysis of particles produced at low momentum. This prohibits adopting the traditional approach, where data rates are reduced through triggering on rare high momentum probes. We explore a new approach based on real-time AI technology, adopt an FPGA-based implementation using a custom designed FELIX-712 board with the Xilinx Kintex Ultrascale FPGA, and deploy the system in the detector readout electronics loop for real-time trigger decision.

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Section: Generation Of the Gnn Ip Corementioning

confidence: 99%

Section: Generation Of the Gnn Ip Corementioning

confidence: 99%

A demonstrator for a real-time AI-FPGA-based triggering system for sPHENIX at RHIC

Kvapil,

Borca-Tasciuc,

Bossi

et al. 2024

J. Inst.

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show abstract

“…FlowGNN [120] is proposed to support generic GNN models for real-time inference applications. By introducing explicit message passing and multi-level parallelism, the authors provide a comprehensive solution for GNN acceleration without sacrificing adaptability.…”

Section: Framework For Fpga-based Acceleratorsmentioning

confidence: 99%

A Survey of Computationally Efficient Graph Neural Networks for Reconfigurable Systems

Kose,

Nunez-Yanez,

Piechocki

et al. 2024

Preprint

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Graph Neural Networks (GNNs) are powerful models capable of managing intricate connections in non-Euclidean data, such as social networks, physical systems, chemical structures, and communication networks. Despite their effectiveness, the large-scale and complex nature of graph data demands substantial computational resources and high performance during both training and inference stages, presenting significant challenges, particularly in the context of embedded systems. Recent studies on GNNs have investigated both software and hardware solutions to enhance computational efficiency. Earlier studies on Deep Neural Networks (DNNs) have indicated that methods like reconfigurable hardware and quantization are beneficial in addressing these issues. Unlike DNN research, studies on efficient computational methods for GNNs are less developed and require more exploration. This survey reviews the latest developments in quantization and FPGA-based acceleration for GNNs, showcasing the capabilities of reconfigurable systems (often FPGAs) to offer customized solutions in environments marked by significant sparsity and the necessity for dynamic load management. It also emphasizes the role of quantization in reducing both computational and memory demands through the use of fixed-point arithmetic and streamlined vector formats. This paper concentrates on low-power, resource-limited devices over general hardware accelerators and reviews research applicable to embedded systems. Additionally, it provides a detailed discussion of potential research gaps, foundational knowledge, obstacles, and prospective future directions.

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“…Traditional Central Processing Units (CPUs), initially designed for sequential tasks, started incorporating SIMD-based graph extensions to enhance parallel processing capabilities [215].Graphics Processing Units (GPUs), with their inherent parallelism, were enhanced with kernel support tailored specifically for graph algorithms [148,174]. Beyond these general-purpose processors, the industry also witnessed the advent of domain-specific accelerators [86,115,153,202], specifically crafted to speedup graph computations, addressing the unique challenges and demands that graph algorithms present.…”

Section: Background and Motivationmentioning

confidence: 99%

“…FlowGNN [153]: FlowGNN introduces a dataflow architecture tailored for the acceleration of GNNs that utilize message-passing mechanisms. The FlowGNN architecture is scalable and supports a broad spectrum of GNN models, featuring a configurable dataflow that simultaneously computes node and edge embeddings as well as facilitates message passing, making it universally applicable across different models.…”

Section: Awb-gcn [65]mentioning

confidence: 99%

Enabling accelerators for graph computing

Shivdikar

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FlowGNN: A Dataflow Architecture for Real-Time Workload-Agnostic Graph Neural Network Inference

Cited by 36 publications

References 38 publications

A demonstrator for a real-time AI-FPGA-based triggering system for sPHENIX at RHIC

A demonstrator for a real-time AI-FPGA-based triggering system for sPHENIX at RHIC

A Survey of Computationally Efficient Graph Neural Networks for Reconfigurable Systems

Enabling accelerators for graph computing

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