Fluorine ion implantation optimization in Saddle-Fin array devices for sub-40-nm DRAM technology

Abstract

Fluorine (F) implantation with different dose post gate oxidation is used for investigating the performance of saddle-fin (S-Fin) array devices including gate-induced drain leakage (GIDL) and retention fail bit counts. Significantly lower retention fail counts of 35% were achieved in using a medium dosage of F implantation. Additional 18% retention fail count reduction was represented by F implantation with A degree tilt angle and 2X keV of energy. Trap passivation by F atoms in the source and the drain areas (S/D) could lead to the improvements.