Focusing processor policies via critical-path prediction

Abstract

Although some instructions hurt performance more than others, current processors typically apply scheduling and speculation as if each instruction was equally costly. Instruction cost can be naturally expressed through the critical path: if we could predict it at run-time, egalitarian policies could be replaced with cost-sensitive strategies that will grow increasingly effective as processors become more parallel.This paper introduces a hardware predictor of instruction criticality and uses it to improve performance. The predictor is both effective and simple in its hardware implementation. The effectiveness at improving performance stems from using a dependence-graph model of the microarchitectural critical path that identifies execution bottlenecks by incorporating both data and machine-specific dependences. The simplicity stems from a token-passing algorithm that computes the critical path without actually building the dependence graph.By focusing processor policies on critical instructions, our predictor enables a large class of optimizations. It can (i) give priority to critical instructions for scarce resources (functional units, ports, predictor entries); and (ii) suppress speculation on non-critical instructions, thus reducing "useless" misspeculations. We present two case studies that illustrate the potential of the two types of optimization, we show that (i) critical-pathbased dynamic instruction scheduling and steering in a clustered architecture improves performance by as much as 21% (10% on average); and (ii) focusing value prediction only on critical instructions improves performance by as much as 5%, due to removing nearly half of the misspeculations.

Compiler Directed Issue Queue Energy Reduction

“…The critical path is modelled as a dependence graph, similar to those proposed by Tullsen and Calder [26] and Fields et al [27]. This is because it provides an accurate representation of the events that occur to instructions as they are dispatched and issued.…”

“…Each edge is weighted with the minimum number of cycles that the dependence takes to be resolved. Unlike in Fields et al [27], control dependences between branches are not modelled because it is assumed that all branches will be predicted correctly. Figure 2 shows an example piece of assembly code and the dependence graph that is formed as the critical path model.…”

Tera-OP Reliable Intelligently Adaptive Processing System (TRIPS) Implementation

“…A performance validation effort showed that performance results from tsim-proc were on average within 4% of those obtained from the RTL-level simulator on our test suite and within 10% on randomly generated test programs. We use the methodology of Fields et al [18] to attribute percentages of the critical path of the program to different microarchitectural activities and partitioning overheads.…”

“…Each instruction passes through a myriad of hardware resources resulting in numerous microarchitectural events during the course of its lifetime-cache misses, branch mispredictions, re-order buffer stalls, port contentions, and data dependence hazards. We developed a critical path analysis tool called tsim critical based on the methodology proposed by Fields et al [18,68].…”

A Hardware and Software Integrated Approach for Adaptive Thread Management in Multicore Multithreaded Microprocessors

“…Recent studies such as Age-based approach [86] and Bottleneck Identification and Scheduling (BIS) [87] were also assisted by the source code, the library and/or the compiler in differentiating the applications. Even though prediction is proposed by Fields et al [88,89], their predictor was Program Counter(PC)-indexed and trace-based. Some other studies, e.g., [90,91], obtained the representative information of the underlying architecture, and then estimated the performance of the applications.…”