Forbidden transition free crosstalk avoidance CODEC design

Abstract

In this work, we present a CODEC design for the forbidden transition free crosstalk avoidance code. Our mapping and coding scheme is based on the Fibonacci numeral system and the mathematical analysis shows that all numbers can be represented by FTF vectors in the Fibonacci numeral system (FNS). The proposed CODEC design is highly efficient, modular and can be easily combined with a bus partitioning technique. We also investigate the implementation issues and our experimental results show that the proposed CODEC complexity is orders of magnitude better compared to the brute force implementation. Compared to the best existing approaches, we achieve a 17% improvement in logic complexity. A high speed design can be achieved through pipelining.

A Bit-Stuffing Algorithm for Crosstalk Avoidance in High Speed Switching

“…We also have developed the associated analysis for these two algorithms. We have shown by both theoretic analysis and simulations that the coding rates of these two bitstuffing algorithms are quite close to the Shannon capacity, and hence are much better than those of the existing forbidden transition codes in the literature, including the Fibonacci representation in [3], [4], and [6]. In this paper, we assume i.i.d.…”

“…Such a Fibonacci representation for forbidden transition codes was also previously addressed in [5]. Recently, an explicit encoding scheme was proposed in [6] to map every input number to its Fibonacci representation for the forbidden transition code in [4]. An alternative mapping that can be used for both forbidden transition codes and forbidden overlap codes was shown in [10].…”

“…An alternative mapping that can be used for both forbidden transition codes and forbidden overlap codes was shown in [10]. However, the overall complexity of the encoders in [6], [10] is O(n 2 ) for a bus with n wires (as there are n − 1 sequential stages in the encoder and each stage requires an O(n)-bit comparator). To further improve the coding rate, two-dimensional forbidden transition codes with block length larger than 1 were proposed in [7], and it was shown that the coding rate could be increased to more than 80%.…”

“…On the other hand, our parallel bit-stuffing algorithm also performs much better than the Fibonacci representation scheme in [3]. Note that the best hardware implementation complexity for implementing the Fibonacci representation scheme for a bus of n wires is O(n 2 ) (see e.g., [6], [26]). This is also much more complex than the O(n) complexity in our scheme.…”

“…Unlike the fixed-length memoryless encoder that uses the Fibonacci representation in [3], [4], and [6], we note that our sequential bit-stuffing algorithm is a variablelength encoder with memory. This is because our sequential bit-stuffing algorithm requires the knowledge of the already coded bits in encoding the next input data bit, and it encodes an input data bit either by one bit (the data bit itself) or by two bits (duplicating the data bit twice by inserting a stuffed bit that is the same as the data bit when the bit-stuffing condition in Algorithm 2(ii-a) is met).…”